ITC 2000:
Atlantic City, NJ, USASession 2:
System Test - Lecture Series
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L. Derere :
Case-based reasoning: diagnosis of faults in complex systems through reuse of experience.
27-34
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Jacob Savir :
On-line and off-line test of airborne digital systems: a reliability study.
35-44
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Session 3:
Ate Software Generation
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Bruce R. Parnas :
Doing it in STIL: intelligent conversion from STIL to an ATE format.
64-71
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Andy Kittross :
Easy mixed signal test creation with test elements and procedures.
72-79
Session 4:
Defect Behavior and Analysis Techniques
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Session 5:
Industrial Applications
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Session 6:
Microprocessor Test
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Farideh Golshan :
Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor.
141-150
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Session 7:
Systems Test
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Session 8:
Practical I DDQ Testing For Deep-Submicron Designs
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Yukio Okuda :
DECOUPLE: defect current detection in deep submicron I_DDQ.
199-206
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Session 9:
Fault Diagnosis Algorithms And Techniques
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Session 10:
Bist Techniques and Applications
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conf/itc/BayraktarogluO00 export record as
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Session 11:
Design Validation:
From Function to Timing
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Session 12:
Defect- Based Test Mehodologies And The Real World - Lecture Series
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Session 13:
Test Techniques For ADCS
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Turker Kuyel ,
Frank Tsay :
Optimal analog trim techniques for improving the linearity of pipeline ADCs.
367-375
Session 14:
Delay Fault Testing
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Haluk Konuk :
On invalidation mechanisms for non-robust delay tests.
393-399
Session 15:
Optimizing Test Effectiveness
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Session 16:
Momory Testing
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Session 17:
Defect - Based Test Methodologies And The Real World - Lecture Series
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Mike Rodgers :
Defect screening challenges in the Gigahertz/Nanometer age: keeping up with the tails of defect behaviors.
464-467
Session 18:
From Tester to Applications - Beginning to End
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Cristo da Costa :
Hardware for production test of RFID interface embedded into chips for smart cards and labels used in contactless applications.
485-491
Session 19:
Test For Crosstalk and Bridging Faults
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Yi Zhao ,
Sujit Dey :
Analysis of interconnect crosstalk defect coverage of test sets.
492-501
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Session 20:
Advances In Test Generation
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Session 21:
Embedde Memories Test And Repair
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Session 22:
Board Test
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Session 23:
Tester Hardware Issues In Leaping To 1GHZ
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Session 24:
Soc Test Solutions
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Steven F. Oakland :
Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits.
628-637
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Session 25:
Low-Power Bist
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Session 26:
Methodology And Tools For Microprocessor Test
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Session 27:
Board Test - lecture Series
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Julia A. Keahey :
Programming of flash with ICT rights and responsibilities.
711-717
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Session 28:
Extraction Test And Diagnosis Of Physical Defects
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conf/itc/StanojevicBWLSB00 export record as
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Session 29:
Use Models Of IEEE P1500
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Session 30:
Quality Bist FOr Logic And FPGA
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Session 31:
Detecting All Types Of Faults TS Quickly
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Session 32:
FPGA- Lecture Series
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Neil G. Jacobson :
Streamlining programmable device and system test using IEEE Std 1532.
847-853
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Session 33:
Test Techniques for Low-Power Optimization
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Lee Whetsel :
Adapting scan architectures for low power operation.
863-872
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Session 34:
Test Access Design For Soc'S
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Session 35:
How Do We Know If Fault Models Areacurate?
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Session 36:
High-Frequence Test Techniques
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conf/itc/YamaguchiSHNRIW00 export record as
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Doug Matthes ,
John Ford :
Technique for testing a very high speed mixed signal read channel design.
965-970
Session 37:
Concurrent Error Detection
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Ramesh Karri ,
Kaijie Wu :
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique.
971-978
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conf/itc/Fernandez-GomezRM00 export record as
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Session 38:
The Final Furdle-Signals And Power To the Dut
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Ulf Pillkahn :
Structural test in a board self test environment.
1005-1012
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Session 39:
Mixed-Signal BIST
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Jiun-Lang Huang ,
Kwang-Ting Cheng :
Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis.
1021-1030
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Session 40:
New Methods For Delay Testing
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conf/itc/KeshavarziRHSSD00 export record as
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conf/itc/PlusquellicGHSC00
Session 41:
Processor Core Test Techniques
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David B. Lavo :
A good excuse for reuse: "open" TAP controller design.
1090-1099
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