ITC 1996:
Washington, DC, USASession 1:
Plenary
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Wojciech Maly :
New and Not-So-New Test Challenges of the Next Decade.
11
Session 2.0:
Automatic Test Generation
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conf/itc/KonijnenburgLG96 export record as
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Session 3.0:
BIST:
Architectures and Generation
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Session 4.0:
New Test Considerations for Mixed-Signal Devices
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Keith Lofstrom :
A Demonstration IC for the P1149.4 Mixed-Signal Test Standard.
92-98
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Koji Asami :
Testing the Digital Modulation of PHS Devices.
99-103
Session 5.0:
Topics in Test Hardware
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Barry D. Kulp :
Testing and Characterizing Jitter in 100BASE-TX and 155.52 Mbit/S ATM Devices with a 1 Gsample/s AWG in an ATE System.
104-111
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Session 6.0:
Practical and Higher-Level Fault Simulation
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conf/itc/KarthikAMPSVdA96
Session 7.0:
BIST Pattern Generation
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Session 8.0:
Testing of Asynchronous Circuits
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Session 9.0:
Industry Impact:
Screeninig, Test, and Measurement Breakthroughs
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Session 10.0:
Fault Simulation and Diagnosis of Delay Faults
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Session 11.0:
Memory Test:
Design for Testability
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conf/itc/SakashitaOSSHTKKYA96
Session 12.0:
Board Test Challenges and Solutions
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Session 13.0:
Delay-Fault Testing 1
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Session 14.0:
Microprocessor Test
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F. Pichon :
Testability Features for a Submicron Voice-coder ASIC.
377-385
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Session 15.0:
An Evolving Mixed-Signal Boundary-Scan Standard
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Lee Whetsel :
Proposal to Simplify Development of a Mixed-Signal Test Standard.
400-409
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Robert J. Russell :
A Method of Extending an 1149.1 Bus for Mixed-Signal Testing.
410-416
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Keith Lofstrom :
Early Capture for Boundary Scan Timing Measurements.
417-422
Session 16.0:
Delay-Fault Testing 2
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Session 17.0:
Software for New Test Strategies
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Session 18.0:
Innovations in Current Testing
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Session 19.0:
Mixed-Signal DFT and Fault Simulation
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conf/itc/DevarayanadurgGS96 export record as
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Session 20.0:
DFT:
Inching Forward with Partial-Scan Design
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Dong Xiang ,
Janak H. Patel :
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information.
548-557
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Session 21.0:
Test Languages and Tools
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Session 22.0:
Application of SPC to IC Design, Manufacturing and Test
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Daniel P. Core :
Risk Assessment Sampling Plans for Non-Standard (Maverick) Material.
595-604
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Session 23.0:
New Techniques for Realistic Faults
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Session 24.0:
Design-for-Testability Inspirations
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Session 25.0:
High Frequency and Timing in ATE
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Michael G. Davis :
The Effect of Periof Generation Techniques on Period Resolution and Waveform Jitter in VLSI Test Systems.
685-690
Session 26.0:
Topics in Test Engineering
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Ralf Stoffels :
Cost Effective Frequency Measurement for Production Testing.
708-716
Session 27.0:
System Test:
Practical Aspects, Partitioning and Simulation
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Wuudiann Ke :
Backplane Interconnect Test in a Boundary-Scan Environment.
717-724
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Session 28.0:
Test Synthesis Solutions
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Session 29.0:
Advanced Fault Modelling Techniques
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Yuyun Liao ,
D. M. H. Walker :
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages.
767-775
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Michael J. Ohletz :
Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits.
776-785
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Session 30.0:
Test Economic Issues
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Session 31.0:
MCM Test:
Methods and Applications
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Andrew Flint :
Three Different MCMs, Three Different Test Strategies.
828-833
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Edward P. Sayre :
MCM Compute Node Thermal Failure - Design or Test Problem?
834-838
Session D1.0:
Design Validation:
Methodologies and Case Studies
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conf/itc/PixleySBPKSBKYN96 export record as
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Marc E. Levitt :
Formal Verification of the UltraSPARCTM Family of Processors via ATPG Methods.
849-856
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Session D2.0:
Hybrid Validation and Test Techniques
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Session D3.0:
Design Validation:
From System Specification to Process Effects
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Session L1:
Unpowered Opens Testing
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Kenneth P. Parker :
Introduction ITC 1996 Lecture Series on Unpowered Opens Testing.
924
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Jack Ferguson :
High Fault Coverage of In-Circuit IC Pin Faults with a Vectorless Test Technique Using Parasitic Transistors.
926
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Joe Wrinn :
Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test, and Radio Frequency Induction Test.
927
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Stig Oresjo :
Unpowered Opens Test with X-Ray Laminography.
929
Session L2:
Practical Aspects of IC Diagnosis & Failure Analysis:
A Walk Through the Process
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David P. Vallett :
An Overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics.
930
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Donald Staab :
Practical Issues of Failure Diagnosis and Analysis in a Fast Cycle Time Environment.
936
Panel 1:
Why Do We Talk about DFT When the Problem is Bad Design and Bad CAD Tools?
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Panel 2:
Asynchronous Design:
Nightmare or Opportunity?
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Panel 5:
DFT for Embedded Cores
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Rochit Rajsuman :
Challenge of the 90's: Testing CoreWareTM Based ASICs.
940
Panel 6:
What Are the Next Generation Test Methodologies for Board and System Test?
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Peter Dziel :
The Need for Complete System Level Test Standardization.
941
Panel 7: Will I-DDQ Testing Leak Away in Deep Sub-Micron Technology?
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