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  Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996. IEEE Computer Society 1996 ISBN 0-7803-3541-4

Session 1: Plenary

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  Walden C. Rhines: Emerging Technologies Drive Domain-Specific Solutions. 10
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  Wojciech Maly: New and Not-So-New Test Challenges of the Next Decade. 11

Session 2.0: Automatic Test Generation

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  Peter Wohl, John A. Waicukauski: Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. 13-20
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  Mitsuo Teramoto, Tomoo Fukazawa: Test Pattern Generation for Circuits with Asynchronous Signals Based on Scan. 21-28
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  M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor: Accelerated Compact Test Set Generation for Three-State Circuits. 29-38
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  Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. 39-47

Session 3.0: BIST: Architectures and Generation

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  Yuejian Wu, Saman Adham: BIST Fault Diagnosis in Scan-Based VLSI Environments. 48-57
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  Pieter M. Trouborst: LFSR Reseeding as a Component of Board Level BIST. 58-67
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  Charles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici: Using ILA Testing for BIST in FPGAs. 68-75
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  Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective BIST Scheme for Datapaths. 76-85

Session 4.0: New Test Considerations for Mixed-Signal Devices

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  Seiji Sasho, Teruhisa Sakata: Four Multi Probing Test for 16 Bit DAC with Vertical Contact Probe Card. 86-91
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  Keith Lofstrom: A Demonstration IC for the P1149.4 Mixed-Signal Test Standard. 92-98
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  Koji Asami: Testing the Digital Modulation of PHS Devices. 99-103

Session 5.0: Topics in Test Hardware

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  Barry D. Kulp: Testing and Characterizing Jitter in 100BASE-TX and 155.52 Mbit/S ATM Devices with a 1 Gsample/s AWG in an ATE System. 104-111
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  Kenji Isawa, Yoshihiro Hashimoto: High-Speed I_DDQ Measurement Circuit. 112-117
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  Solomon Max: Extending Calibration Intervals. 118-126
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  Steven DeFoster, Dennis Karst, Matthew Peterson, Paul Sendelbach, Kirk Kottschade: Manufacturing Test of Fiber Channel Communications Cards and Optical Subassemblies. 127-134

Session 6.0: Practical and Higher-Level Fault Simulation

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  Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski: A Universal Technique for Accelerating Simulation of Scan Test Patterns. 135-141
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  Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz: On Potential Fault Detection in Sequential Circuits. 142-149
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  Weiwei Mao, Ravi K. Gulati: Improving Gate Level Fault Coverage by RTL Fault Grading. 150-159
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  Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham: Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. 160-166

Session 7.0: BIST Pattern Generation

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  Nur A. Touba, Edward J. McCluskey: Altering a Pseudo-Random Bit Sequence for Scan-Based BIST. 167-175
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  Mohammed F. AlShaibi, Charles R. Kime: MFBIST: A BIST Method for Random Pattern Resistant Circuits. 176-185
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  Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski: Two-Dimensional Test Data Decompressor for Multiple Scan Designs. 186-194
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  Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig: Mixed-Mode BIST Using Embedded Processors. 195-204

Session 8.0: Testing of Asynchronous Circuits

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  Marly Roncken, Eric Bruls: Test Quality of Asynchronous Circuits: A Defect-oriented Evaluation. 205-214
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  Marly Roncken, Emile H. L. Aarts, Wim F. J. Verhaegh: Optimal Scan for Pipelined Testing: An Asynchronous Foundation. 215-224
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  Volker Schöber, Thomas Kiel: An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention. 225-231
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  Montek Singh, Steven M. Nowick: Synthesis-for-Initializability of Asynchronous Sequential Machines. 232-241

Session 9.0: Industry Impact: Screeninig, Test, and Measurement Breakthroughs

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  Timothy R. Henry, Thomas Soo: Burn-in Elimination of a High Volume Microprocessor Using I_DDQ. 242-249
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  Peter C. Maxwell, Robert C. Aitken, Kathleen R. Kollitz, Allen C. Brown: I_DDQ and AC Scan: The War Against Unmodelled Defects. 250-258
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  Alan W. Righter, Jerry M. Soden, Richard W. Beegle: High Resolution I_DDQ Characterization and Testing - Practical Issues. 259-268
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  K. Ozaki, H. Sekiguchi, S. Wakana, Y. Goto, Y. Umehara, J. Matsumoto: Novel Optical Probing System with Submicron Spatial Resolution for Internal Diagnosis of VLSI Circuits. 269-275

Session 10.0: Fault Simulation and Diagnosis of Delay Faults

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  Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. 276-285
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  Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. 286-293
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  Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs: Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis. 294-302

Session 11.0: Memory Test: Design for Testability

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  Piero Olivo, Marcello Dalpasso: Self-Learning Signature Analysis for Non-Volatile Memory Testing. 303-308
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  Anne Meixner, Jash Banik: Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique. 309-318
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  Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe: A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. 319-324

Session 12.0: Board Test Challenges and Solutions

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  Christophe Vaucher, Louis Balme: Analog/Digital Testing of Loaded Boards Without Dedicated Test Points. 325-332
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  Mick Tegethoff, Kenneth P. Parker, Ken Lee: Opens Board Test Coverage: When is 99% Really 40%? 333-339
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  D. Eugene Wedge, Tom Conner: A Roadmap for Boundary-Scan Test Reuse. 340-346

Session 13.0: Delay-Fault Testing 1

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  Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy: Local Transformations and Robust Dependent Path Delay. 347-356
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  Irith Pomeranz, Sudhakar M. Reddy: On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. 357-366
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  Jonathan T.-Y. Chang, Edward J. McCluskey: Detecting Delay Flaws by Very-Low-Voltage Testing. 367-376

Session 14.0: Microprocessor Test

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  F. Pichon: Testability Features for a Submicron Voice-coder ASIC. 377-385
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  Hugo Cheung, Sandeep K. Gupta: A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. 386-395
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  Wayne M. Needham, Naga Gollakota: DFT Strategy for Intel Microprocessors. 396-399

Session 15.0: An Evolving Mixed-Signal Boundary-Scan Standard

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  Lee Whetsel: Proposal to Simplify Development of a Mixed-Signal Test Standard. 400-409
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  Robert J. Russell: A Method of Extending an 1149.1 Bus for Mixed-Signal Testing. 410-416
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  Keith Lofstrom: Early Capture for Boundary Scan Timing Measurements. 417-422

Session 16.0: Delay-Fault Testing 2

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  Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar: Identification and Test Generation for Primitive Faults. 423-432
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  G. M. Luong, D. M. H. Walker: Test Generation for Global Delay Faults. 433-442
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  Dimitrios Karayiannis, Spyros Tragoudas: ATPD: An Automatic Test Pattern Generator for Path Delay Faults. 443-452

Session 17.0: Software for New Test Strategies

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  Yasuji Oyama, Toshinobu Kanai, Hironobu Niijima: Scan Design Oriented Test Technique for VLSI's Using ATE. 453-460
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  Klaus Helmreich, G. Reinwardt: Virtual Test of Noise and Jitter Parameters. 461-470
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  Yuhai Ma, Wanchun Shi: A Novel Approach to the Analysis of VLSI Device Test Programs. 471-480

Session 18.0: Innovations in Current Testing

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  James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan: Digital Integrated Circuit Testing using Transient Signal Analysis. 481-490
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  Jos van Sas, Urbain Swerts, Marc Darquennes: Towards an Effective I_DDQ Test Vector Selection and Application Methodology. 491-500
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  Theo J. Powell, James R. Pair, Bernard G. Carbajal III: Correlating Defects to Functional and I_DDQ Tests. 501-510

Session 19.0: Mixed-Signal DFT and Fault Simulation

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  Thomas Olbrich, Jordi Pérez, Ian A. Grout, Andrew M. D. Richardson, Carles Ferrer: Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICs. 511-520
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  Giri Devarayanadurg, Prashant Goteti, Mani Soma: Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICs. 521-527
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  Evan M. Hawrysh, Gordon W. Roberts: An Integration of Memory-Based Analog Signal Generation into Current DFT Architectures. 528-537

Session 20.0: DFT: Inching Forward with Partial-Scan Design

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  Vamsi Boppana, W. Kent Fuchs: Partial Scan Design Based on State Transition Modeling. 538-547
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  Dong Xiang, Janak H. Patel: A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information. 548-557
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  Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. 558-564

Session 21.0: Test Languages and Tools

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  Anthony Taylor, Gregory A. Maston: Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms. 565-570
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  Naim Ben Hamida, Khaled Saab, David Marche, Bozena Kaminska, Guy Quesnel: LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits. 571-580
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  Ilene Burnstein, Taratip Suwannasart, C. Robert Carlson: Developing a Testing Maturity Model for Software Test Process Evaluation and Improvement. 581-589

Session 22.0: Application of SPC to IC Design, Manufacturing and Test

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  Von-Kyoung Kim, Mick Tegethoff, Tom Chen: ASIC Yield Estimation at Early Design Cycle. 590-594
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  Daniel P. Core: Risk Assessment Sampling Plans for Non-Standard (Maverick) Material. 595-604
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  Jos van der Peet, Ger van Boxem: SPC on the IC-Production Test Process. 605-610

Session 23.0: New Techniques for Realistic Faults

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  David B. Lavo, Tracy Larrabee, Brian Chess: Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis. 611-619
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  F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos, João Paulo Teixeira: Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation. 620-628
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  Li-C. Wang, M. Ray Mercer, Thomas W. Williams: Using Target Faults To Detect Non-Tartget Defects. 629-638

Session 24.0: Design-for-Testability Inspirations

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  Sandeep Bhatia, Tushar Gheewala, Prab Varma: A Unifying Methodology for Intellectual Property and Custom Logic Testing. 639-648
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  Nagesh Tamarapalli, Janusz Rajski: Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. 649-658
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  Robert B. Norwood, Edward J. McCluskey: Orthogonal Scan: Low-Overhead Scan for Data Paths. 659-668

Session 25.0: High Frequency and Timing in ATE

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  Kazunori Chihara, Takashi Sekino, Koji Sasaki: An Application of Photoconductive Switch for High-Speed Testing. 669-676
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  Hideaki Imada, Kenichi Fujisaki, Toshimi Ohsawa, Masaru Tsuto: Generation Technique of 500MHz Ultra-High Speed Algorithmic Pattern. 677-684
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  Michael G. Davis: The Effect of Periof Generation Techniques on Period Resolution and Waveform Jitter in VLSI Test Systems. 685-690

Session 26.0: Topics in Test Engineering

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  Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell: Analysis and Detection of Timing Failures in an Experimental Test Chip. 691-700
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  David Potts, Roger Griesmer: A Unique Methodology for At-Speed Test of cDSP^TM and ASIC Devices. 701-707
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  Ralf Stoffels: Cost Effective Frequency Measurement for Production Testing. 708-716

Session 27.0: System Test: Practical Aspects, Partitioning and Simulation

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  Wuudiann Ke: Backplane Interconnect Test in a Boundary-Scan Environment. 717-724
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  Yves Le Traon, Ghassan Al Hayek, Chantal Robach: Testability-Oriented Hardware/Software Partitioning. 725-731
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  Pablo Sanchez, Isabel Hidalgo: System Level Fault Simulation. 732-740

Session 28.0: Test Synthesis Solutions

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  Tom Eberle, Robert McVay, Chris Meyers, Jason Moore: ASIC BIST Synthesis: A VHDL Approach. 741-750
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  James Beausang, Chris Ellingham, Markus Robinson: Integrating Scan into Hierarchical Synthesis Methodologies. 751-756
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  Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani: Synthesis of Self-Testing Finite State Machines from High-Level Specifications. 757-766

Session 29.0: Advanced Fault Modelling Techniques

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  Yuyun Liao, D. M. H. Walker: Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. 767-775
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  Michael J. Ohletz: Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits. 776-785
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  Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly: I_DDQ Test: Sensitivity Analysis of Scaling. 786-792

Session 30.0: Test Economic Issues

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  Hiromu Fujioka, Koji Nakamae, Akio Higashi: Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost. 793-799
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  Felix Frayman, Mick Tegethoff, Brenton White: Issues in Optimizing the Test Process - A Telecom Case Study. 800-808
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  Matthew Boutin, Peter Dziel: Application of Boundary Scan in a Fault Tolerant Computer System. 809-817

Session 31.0: MCM Test: Methods and Applications

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  Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian: Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates. 818-827
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  Andrew Flint: Three Different MCMs, Three Different Test Strategies. 828-833
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  Edward P. Sayre: MCM Compute Node Thermal Failure - Design or Test Problem? 834-838

Session D1.0: Design Validation: Methodologies and Case Studies

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  Carl Pixley, Noel R. Strader, W. C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen: Commercial Design Verification: Methodology and Tools. 839-848
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  Marc E. Levitt: Formal Verification of the UltraSPARC^TM Family of Processors via ATPG Methods. 849-856
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  Neeta Ganguly, Magdy S. Abadir, Manish Pandey: PowerPC^TM Array Verification Methodology using Formal Techniques. 857-864

Session D2.0: Hybrid Validation and Test Techniques

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  Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser: An ATPG-Based Framework for Verifying Sequential Equivalence. 865-874
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  Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote: A Unified Framework for Design Validation and Manufacturing Test. 875-884
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  Ghassan Al Hayek, Chantal Robach: From Specification Validation to Hardware Testing: A Unified Method. 885-893

Session D3.0: Design Validation: From System Specification to Process Effects

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  Duncan Clarke, Insup Lee: Testing-Based Analysis of Real-Time System Models. 894-903
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  Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li: Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. 904-913
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  Melvin A. Breuer, Sandeep K. Gupta: Process-Aggravated Noise (PAN): New Validation and Test Problems. 914-923

Session L1: Unpowered Opens Testing

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  Kenneth P. Parker: Introduction ITC 1996 Lecture Series on Unpowered Opens Testing. 924
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  Ted T. Turner: Capacitive Leadframe Testing. 925
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  Jack Ferguson: High Fault Coverage of In-Circuit IC Pin Faults with a Vectorless Test Technique Using Parasitic Transistors. 926
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  Joe Wrinn: Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test, and Radio Frequency Induction Test. 927
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  Anthony J. Suto: Analog AC Harmonic Method for Detecting Solder Opens. 928
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  Stig Oresjo: Unpowered Opens Test with X-Ray Laminography. 929

Session L2: Practical Aspects of IC Diagnosis & Failure Analysis: A Walk Through the Process

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  David P. Vallett: An Overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics. 930
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  Robert C. Aitken: Modelling the Unmodellable: Algorithmic Fault Diagnosis. 931
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  Keith Baker, Jos van Beers: Shmoo Plots - the Black Art of IC Test. 932-933
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  Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Jones, Jayashree Saxena: Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. 934
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  Jerry M. Soden, Richard E. Anderson, Christopher L. Henderson: IC Failure Analysis Tools and Techniques - Macig, Mystery, and Science. 935
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  Donald Staab: Practical Issues of Failure Diagnosis and Analysis in a Fast Cycle Time Environment. 936

Panel 1: Why Do We Talk about DFT When the Problem is Bad Design and Bad CAD Tools?

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  William R. Simpson: The Key to Concurrent Engineering is Design Tools. 937

Panel 2: Asynchronous Design: Nightmare or Opportunity?

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  Stephen B. Furber: The Return of Asynchronous Logic. 938
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  Marly Roncken: Asynchronous Design: Working the Fast Lane. 939

Panel 5: DFT for Embedded Cores

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  Rochit Rajsuman: Challenge of the 90's: Testing CoreWare^TM Based ASICs. 940

Panel 6: What Are the Next Generation Test Methodologies for Board and System Test?

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  Peter Dziel: The Need for Complete System Level Test Standardization. 941

Panel 7: Will I-DDQ Testing Leak Away in Deep Sub-Micron Technology?

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  Manoj Sachdev: Deep Sub-micron I_DDQ Test Options. 942