ITC 1992:
Baltimore, MD, USASession 1:
Plenary
Keynote Address
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Invited Address
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Session 2:
Test Generation from Switch to Multiprocessor
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Session 3:
Test Architecture
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Jim Chapman :
High-Performance CMOS-Based VLSI Testers: Timing Control and Compensation.
59-67
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Akinori Maeda :
The Advanced Test System Architecture Provides Fast and Accurate Test for a High Resolution ADC.
68-75
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Session 4:
Boundary Scan:
Device Level Applications
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Wayne T. Daniel :
Design Verification of a High Density Computer Using IEEE 1149.1.
84-90
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John Andrews :
IEEE 1149.1 Applied to Mixed TTL-ECL and Differential Logic.
91-95
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Session 5:
New Approaches to BIST
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Session 6:
Should We Go Beyond Stuck-at Faults to Improve Quality?
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Roger Perry :
IDDQ Testing in CMOS Digital ASIC's - Putting it All Together.
151-157
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K. Sawada ,
S. Kayano :
An Evaluation of IDDQ Versus Conventional Testing for CMOS Sea-of-Gate IC's.
158-167
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Session 7:
Testing and Diagnosis of Sequential Circuits
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Session 8:
Boundary Scan:
System Level Design and Application
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Lee Whetsel :
A Proposed Method of Accessing 1149.1 in a Backplane Environment.
206-216
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Session 9:
New Test and Development Methods
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Haruo Kato :
CCD Image Sensor Test Using Cellular Automation-Type Pattern Recognition System.
242-246
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Session 10 - Panel:
MCM Testing:
Bringing MCMs into the Mainstream
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Session 11 - Panel:
The Agony of Short Time to Market
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Keith Baker :
Time-to-Market: An Issue in Mixed-signal vs. Analogue.
254
Session 12 - Panel:
Does Object-Oriented Programming Fit in Real World ATE?
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Richard S. Levy :
Does Object-Oriented Programming Fit in the Real World of ATE?
255-256
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James R. Ward :
The Reality of Object Oriented Solutions for ATE.
257-258
Session 13 - Panel:
Memory Testing Technology in a Gigabit Age in Japan
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Session 14:
IC Manufacturer Practical Quality Improvement Techniques
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Robert Trahan ,
Rex Kiang :
An Analysis of the Die Testing Process Using Taguchi Techniques and Circuit Diagnostics.
260-269
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Sarkis Ourfalian :
Successful Implementation of SPC in Semiconductor Final Test.
275-282
Session 15:
Scan Design:
More Bang for Less Bucks
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Session 16:
Analog to Digital Converter Testing
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Session 17:
Board Test
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Gaspare Pantano ,
Dave Rolince :
VECTOR (Virtual Edge Connector Test): A Strategy to Increase TPS Fault Coverage Without Adding Test Vectors.
345-351
Session 18:
Three Approaches to Increase Good Product Shipped
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Session 19:
Boundary Scan:
Board Level Design and Analysis
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Session 20:
Error Modeling and Design for Test in Mixed Signal Devices
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Session 21:
ATE Timing Subsystems
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R. Warren Necoechea :
High Performance Monolithic Verniers for VLSI Automatic Test Equipment.
422-430
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Gary Fehr :
Timing-Per-Pin Flexibility at Shared-Resource Cost.
431-438
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Timothy Alton :
TGEN: Flexible Timing Generator Architecture.
439-443
Session 22:
Test Data Management
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Session 23:
Bridging and Other Faults in CMOS Circuits
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Session 24:
BIST Design Techniques
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Session 25:
ATE Timing Accuracy and Calibration
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Session 26 - Panel:
Systems Testing - The Home for All Product Test Planning?
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Session 27 - Panel:
Is IC Burn-In or Burned-Out - Part 2
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Session 28 - Panel:
Software Testing:
Opportunity and Nightmare
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Session 29 - Panel:
P1149.4 Mixed-Signal Test Bus Framework Proposals
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B. R. Wilkins :
A Structure for Board-Level Mixed-Signal Testability.
556-557
Session 30:
System Issues in Delay Testing
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conf/itc/KonemannBCGGKMTIRW92 Bernd Könemann ,
J. Barlow ,
Paul Chang ,
R. Gabrielson ,
C. Goertz ,
Brion L. Keller ,
Kevin McCauley ,
J. Tischer ,
Vijay S. Iyengar ,
Barry K. Rosen ,
T. Williams :
Delay Test: The Next Frontier for LSSD Test Systems.
578-587
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Session 31:
Memory Design and Test Techniques
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Tom Chen ,
Glen Sunada :
A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories.
623-631
Session 32:
Advances in Design for Testability Techniques
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Session 33:
Microprocessor Testing Case Studies
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Marcus Rimén ,
Joakim Ohlsson :
A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection.
696-704
Session 34:
Advanced Delay Testing
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Jacob Savir :
Skewed-Load Transition Test: Part 1, Calculus.
705-713
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Session 35: Test Synthesis
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Session 36: CAE for Defect Detection and I-DDQ Testing
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Robert C. Aitken :
A Comparison of Defect Models for Fault Location with IDDQ Measurements.
778-787
Session 37:
Special Topics in Mixed Signal Testing
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Takashi Kido :
In-Process Inspection Technique for Active-Matrix LCD Panels.
795-799
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Session 38:
Test Generation Techniques
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Session 39:
Contactless Probing
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Alan C. Noble :
IDA: A Tool for Computer-Aided Failure Analysis.
848-853
Session 40:
Developments in CAD to Test
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Session 41:
Unique Design, Fault, and Defect Issues
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conf/itc/Rodriguez-MontanesFB92
Session 42:
Testing Computer Software
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conf/itc/BurnsteinJMTGL92
Session 43:
High Performance Probing
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Daniel T. Hamling :
A 3GHz, 144 Point Probe Fixture for Automatic IC Wafer Testing.
940-947
Session 44:
Self-Checking, Concurrent Testing, and Self-repair
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Pinaki Mazumder :
An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays.
968-977
Session 45:
System Testing
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1991 Best Paper Award
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data released under the ODC-BY 1.0 license
