ITC 1990:
Washington,
DC,
USA
Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990.
IEEE Computer Society 1990, ISBN 0-8186-9064-
- Akihiko Yamada:
Challenge of design and test of ultra-large-scale circuits.
23
- Janusz Rajski, Henry Cox:
A method to calculate necessary assignments in algorithmic test pattern generation.
25-34
- Miron Abramovici, David T. Miller, R. Henning:
Global cost functions for test generation.
35-43
- John A. Waicukauski, Paul A. Shupe, David Giramma, Arshad Matin:
ATPG for ultra-large structured designs.
44-51
- Paolo Camurati, Davide Medina, Paolo Prinetto, Matteo Sonza Reorda:
A diagnostic test pattern generation algorithm.
52-58
- David K. Oka:
Analog test requirements of linear echo cancellation ISDN devices.
59-67
- Luis A. Bonet, J. Ganger, Jim Girardeau, Carlos Greaves, M. Pendleton, David Yatim:
Test features of the MC145472 ISDN U-transceivers.
68-79
- Billy W. Sprinkle:
Fast and accurate testing of ISDN S/T interface devices using pseudo error rate techniques.
80-85
- Kenneth Lanier:
ATE-based functional ISDN testing.
86-94
- Gordon Sapp:
ASSIST (Allied Signal's Standardized Integrated Scan Test).
95-102
- Endre F. Sarkany, Robert F. Lusch:
Innovative techniques for improved testability.
103-108
- John Sweeney:
Testability implemented in the VAX 6000 model 400.
109-114
- Chul J. Choi:
Scan based guided probe technology delivers Cyclone to the market.
115-119
- David L. Landis, Padmaraj Singh:
Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration.
120-126
- Johann Maierhofer:
Hierarchical self-test concept based on the JTAG standard.
127-134
- Lee Whetsel:
Event qualification: a gateway to at-speed system testing.
135-141
- C. Thomas Glover:
Mixed-mode ATPG under input constraints.
142-151
- Chau-Chin Su, Charles R. Kime:
Multiple path sensitization for hierarchical circuit testing.
152-161
- Kwang-Ting Cheng, Jing-Yang Jou:
Functional test generation for finite state machines.
162-168
- T. Michael Souders, Gerard N. Stenbakken:
A comprehensive approach for modeling and testing analog and mixed-signal devices.
169-176
- Robert Van Rijsinge, A. A. R. M. Haggenburg, C. de Vries, Hans Wallinga:
From specification to measurement: the bottleneck in analog industrial testing.
177-182
- Mani Soma:
A design-for-test methodology for active analog filters.
183-192
- Alan C. Walker:
Stress profile derivation-an empirical approach.
193-207
- Frank J. Langley, C. A. Robinson, R. A. Passero:
Automatic electro-optical testing of automobile dashboard displays in a factory environment.
208-213
- Durwin Gill:
Time margin issues in disk drive testing.
214-221
- Kenneth P. Parker, Stig Oresjo:
A language for describing boundary-scan devices.
222-234
- Frans de Jong:
Boundary scan test used at board level: moving towards reality.
235-242
- Don Sterba, Andy Halliday, Don McClean:
ATPG issues for board designs implementing boundary scan.
243-251
- Steven D. McEuen:
Why, IDDQ? [CMOS IC testing].
252
- Keith Baker, Bas Verhelst:
IDDQ testing because `zero defects isn't enough': a Philips perspective.
253-254
- Jerry M. Soden, Ronald R. Fritzemeier, Charles F. Hawkins:
Zero defects or zero stuck-at faults-CMOS IC process improvement with IDDQ.
255-256
- Wojciech Maly:
Current testing.
257
- Al Lowenstein, Steve Schlosser, Greg Winter:
Concurrent engineering.
258-259
- Melvin A. Breuer:
Obstacles and an approach towards concurrent engineering.
260-261
- Noel E. Donlin:
QML (qualified manufacturing line): a method of providing high quality integrated circuits.
262-263
- Robert W. Thomas:
Test engineers role in QML.
264
- Janusz Rajski, Jagadeesh Vasudevamurthy:
Testability preserving transformations in multi-level logic synthesis.
265-273
- Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Sequential logic synthesis for testability using register-transfer level descriptions.
274-283
- Srinivas Devadas, Kurt Keutzer:
Design of integrated circuits fully testable for delay-faults and multifaults.
284-293
- Mark F. Lefebvre:
Functional test and diagnosis: a proposed JTAG sample mode scan tester.
294-303
- Matthew L. Fichtenbaum, Gordon D. Robinson:
Scan test architectures for digital board testers.
304-310
- Chi W. Yau, Najmi T. Jarwala:
The boundary-scan master: target applications and functional requirements.
311-315
- Michael Nicolaidis:
Efficient UBIST implementation for microprocessor sequencing parts.
316-326
- Yasuyuki Nozuyama:
Realization of an efficient design verification test used on a microinstruction controlled self test.
327-336
- Philip E. Bishop, Grady Giles, Sudarshan Iyengar, C. Thomas Glover, Wai-on Law:
Testability considerations in the design of the MC68340 Integrated Processor Unit.
337-346
- Sheng-Jen Tsai, Wha-Joon Lee:
A high-speed pin-memory architecture using multiport dynamic RAMs.
347-354
- Burnell West, Tom Napier:
Sequencer Per Pin test system architecture.
355-361
- David C. Keezer:
Multiplexing test system channels for data rates above 1 Gb/s.
362-368
- Bong-Hee Park, Premachandran R. Menon:
Design of scan-testable CMOS sequential circuits.
369-376
- Vivek Chickermane, Janak H. Patel:
An optimization based approach to the partial scan design problem.
377-386
- Weiwei Mao, Michael D. Ciletti:
Arrangement of latches in scan-path design to improve delay fault coverage.
387-393
- Grant L. Castrodale, Apostolos Dollas, William T. Krakow:
An interactive environment for the transparent logic simulation and testing of integrated circuits.
394-403
- Michiaki Emori, Takashi Aikyo, Yasuhide Machida, Jun-ichi Shikatani:
ASIC CAD system based on hierarchical design-for-testability.
404-409
- Ajit Agrawal, Debashis Bhattacharya:
CMP3F: a high speed fault simulator for the Connection Machine.
410-416
- Kuen-Jong Lee, Melvin A. Breuer:
On the charge sharing problem in CMOS stuck-open fault testing.
417-426
- Ronald R. Fritzemeier, Jerry M. Soden, R. Keith Treece, Charles F. Hawkins:
Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets.
427-435
- F. Joel Ferguson, Martin Taylor, Tracy Larrabee:
Testing for parametric faults in static CMOS circuits.
436-443
- Leslie Ackner, Mark R. Barber:
Frequency enhancement of digital VLSI test systems.
444-451
- Phil Burlison:
Criteria for analyzing high frequency testing performance of VLSI automatic test equipment.
452-461
- Donald F. Murray, C. Michael Nash:
Critical parameters for high-performance dynamic response measurements.
462-471
- Math Muris:
Integrating boundary scan test into an ASIC design flow.
472-477
- J. Morris Chang:
A study of the optimization of DC parametric tests.
478-487
- Venkata R. Immaneni, Srinivas Raman:
Direct access test scheme-design of block and core cells for embedded ASICs.
488-492
- H. Kato:
Color reproduction test for CCD image sensors.
493-497
- Jack Weimer, Kevin Baade, John Fitzsimmons, Brian Lowe:
A rapid dither algorithm advances A/D converter testing.
498-507
- Jun Kurita, Nobuyuki Kasuga, Kiyoyasu Hiwada:
An advanced test system architecture for synchronous and asynchronous control of mixed signal device testing.
508-513
- Anthony Taylor:
An analysis of ATE computational architecture.
514-519
- Jens Leenstra, Lambert Spaanenburg:
Hierarchical test assembly for macro based VLSI design.
520-529
- Don Organ:
enVision: the inside story.
530-536
- Ove Brynestad, Einar J. Aas, Anne E. Vallestad:
State transition graph analysis as a key to BIST fault coverage.
537-543
- Albrecht P. Stroele, Hans-Joachim Wunderlich:
Error masking in self-testable circuits.
544-552
- John C. Chan, Jacob A. Abraham:
A study of faulty signatures using a matrix formulation.
553-561
- L. Klein, J. Bridgeman:
An architecture for high-speed analog in-circuit testing.
562-564
- Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu:
Diagnosis for wiring interconnects.
565-571
- Gordon D. Robinson, John G. Deshayes:
Interconnect testing of boards with partial boundary scan.
572-581
- Bulent I. Dervisoglu:
Towards a standard approach for controlling board-level test functions.
582-590
- Ravi Rastogi, Kenneth F. Sierzega:
A new approach to mixed-signal diagnosis.
591-597
- Ram Bobba, B. Stevens:
Fast embedded A/D converter testing using the microcontroller's resources.
598-604
- David T. Crook:
A fourth generation analog incircuit program generator.
605-612
- Yasuo Furukawa, Makoto Kimura, Masao Sugai, Shinichi Kimura, Michael Purtell:
Jitter minimization technique for mixed signal testing.
613-619
- Y. M. Mastoris, P. D. Nash:
Networking verification process and environments: an extension of the product realization process for new network capabilities.
620-626
- Miroslaw Malek, Banu Özden:
Optimized testing of meshes.
627-637
- Mark G. Karpovsky, Lev B. Levitin, Feodor S. Vainstein:
Identification of faulty processing elements by space-time compression of test responses.
638-647
- Don R. Allen:
Failure probability algorithm for test systems to reduce false alarms.
648-656
- Jacob Savir, William H. McAnney:
A multiple seed linear feedback shift register.
657-659
- Fidel Muradali, Vinod K. Agarwal, Benoit Nadeau-Dostie:
A new procedure for weighted random built-in self-test.
660-669
- Sybille Hellebrand, Hans-Joachim Wunderlich, Oliver F. Haberl:
Generating pseudo-exhaustive vectors for external testing.
670-679
- Chau-Chin Su, Charles R. Kime:
Computer-aided design of pseudoexhaustive BIST for semiregular circuits.
680-689
- Leendert M. Huisman, Raja Daoud:
Fault simulation of logic designs on parallel processors with distributed memory.
690-697
- William H. Nicholls, Arnold W. Nordsieck, Mani Soma:
Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test cases.
698-705
- Ohyoung Song, Premachandran R. Menon:
Parallel pattern fault simulation based on stem faults in combinational circuits.
706-711
- Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal:
An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited.
712-720
- Robert L. Hickling:
Extending binary searches to two and three dimensions [IC testing].
721-725
- Jacob Savir:
AC product defect level and yield loss.
726-738
- R. Mehtani, Keith Baker, C. M. Huizer, P. J. Hynes, Jos van Beers:
Macro-testability and the VSP.
739-748
- Michael G. Gallup, William Ledbetter Jr., Ralph McGarity, Steve McMahan, Kenneth Scheuer, Clark G. Shepard, Lal Sood:
Testability features of the 68040.
749-757
- Naga Gollakota, Ahmad Zaidi:
Fault grading the Intel 80486.
758-761
- Paul H. Bardell:
Analysis of cellular automata used as pseudorandom pattern generators.
762-768
- Jos van Sas, Francky Catthoor, Hugo De Man:
Cellular automata based self-test for programmable data paths.
769-778
- Kazuhiko Iwasaki, Noboru Yamaguchi:
Design of signature circuits based on weight distributions of error-correcting codes.
779-785
- Sheldon B. Akers, Sungju Park, Balakrishnan Krishnamurthy, Ashok Swaminathan:
Why is less information from logic simulation more useful in fault simulation?
786-800
- Fadi Maamari, Janusz Rajski:
The dynamic reduction of fault simulation.
801-808
- Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Single-fault fault collapsing analysis in sequential logic circuits.
809-814
- Hiroki Koike, Toshio Takeshima, Masahide Takada:
A BIST scheme using microprogram ROM for large capacity memories.
815-822
- Thierry Viacroze, Marc Lequeux:
Analysis of failures on memories using expert system techniques.
823-832
- Pinaki Mazumder, Jih-Shyr Yih:
A novel built-in self-repair approach to VLSI memory yield enhancement.
833-841
- Thomas M. Storey, Wojciech Maly:
CMOS bridging fault detection.
842-851
- V. Chandramouli, Ravi K. Gulati, Ramaswami Dandapani, Deepak K. Goel:
Bridging faults and their implication to PLAs.
852-859
- Steven D. Millman, Edward J. McCluskey, John M. Acken:
Diagnosing CMOS bridging faults with stuck-at fault dictionaries.
860-870
- Yervant Zorian, André Ivanov:
EEODM: An effective BIST scheme for ROMs.
871-879
- Narumi Sakashita, Hisako Sawai, Eiichi Teraoka, Toshiki Fugiyama, Toru Kengaku, Yukihiko Shimazu, Takeshi Tokuda:
Built-in self-test in a 24 bit floating point digital signal processor.
880-885
- Thomas M. Schwair, Hartmut C. Ritter:
Complete self-test architecture for a coprocessor [cryptography].
886-890
- Joseph A. Mielke, Keith A. Pope:
High-speed fixture interconnects for mixed-signal IC testing.
891-895
- Samuel Schleifer:
Improving wafer sort yields with radius-tip probes.
896-899
- T. Tada, R. Takagi, S. Nakao, M. Hyozo, T. Arakawa, K. Sawada, M. Ueda:
A fine pitch probe technology for VLSI wafer testing.
900-906
- Paul Mullenix:
The capability of capability indices with an application to guardbanding in a test environment.
907-915
- Michael P. Palumbo:
Technique for transfer of analog prototypes (DV's) to production.
916-923
- Yolanda T. Hadeed, Kevin T. Lewis:
The use of tolerance intervals in the characterization of semiconductor devices.
924-928
- R. Meershoek, Bas Verhelst, Rory McInerney, Loek Thijssen:
Functional and IDDQ testing on a static RAM.
929-937
- Ashish Pancholy, Janusz Rajski, Larry J. McNaughton:
Empirical failure analysis and validation of fault models in CMOS VLSI.
938-947
- Etienne Sicard, Kozo Kinoshita:
On the evaluation of process-fault tolerance ability of CMOS integrated circuits.
948-954
- Xiaoqing Wen, Kozo Kinoshita:
A testable design of logic circuits under highly observable condition.
955-963
- Tsu-Wei Ku, Mani Soma:
Minimal overhead modification of iterative logic arrays for C-testability.
964-969
- Rafic Z. Makki, Krisbnm Palaniswami:
Practical partitioning for testability with time-shared boundary scan.
970-977
- Larry Moran, Robert Hillman, Phil Burlison, Tom Gurda:
The Waveform and Vector Exchange Specification (WAVES).
978-987
- William W. Sebesta, Bas Verhelst, Michael G. Wahl:
Development of a new standard for test.
988-993
- Masahiro Handa, Russel L. Steinweg:
Wave+: An easy-to-use vector generation language for compilers.
994-999
- J. Gartner, B. Driscoll, Donato O. Forlenza, Orazio P. Forlenza, Timothy J. Koprowski, T. Lizambri, R. Olsen, S. Robertson, P. Ryan, A. Walter:
Weighted random test program generation for a per-pin tester.
1000-1005
- Robert B. Elo:
An empirical relationship between test transparency and fault coverage.
1006-1011
- Raoul Velazco, Catherine Bellon, Bernard Martinet:
Failure coverage of functional test methods: a comparative experimental evaluation.
1012-1017
- Richard H. Williams, Charles F. Hawkins:
Errors in testing.
1018-1027
- Roberto Menozzi, Mattia Lanzoni, Luca Selmi, Bruno Riccò:
An improved procedure to test CMOS ICs for latch-up.
1028-1034
- Mitsuru Shinagawa, Tadao Nagatsuma:
A picosecond external electro-optic prober using laser diodes.
1035-1039
- Arthur Hu, Hironobu Niijima:
New approach to integrate LSI design databases with e-beam tester.
1040-1048
- Norio Kuji, Kiyoshi Matsumoto:
Marginal fault diagnosis based on e-beam static fault imaging with CAD interface.
1049-1054
- Prab Varma:
TDRC-a symbolic simulation based design for testability rules checker.
1055-1064
- Takuji Ogihara, Yasushi Koseko, Genichi Yonemori, Hiroyuki Kawai:
Testable design and support tool for cell based test.
1065-1071
- Harald Gundlach, Klaus D. Müller-Glaser:
On automatic testpoint insertion in sequential circuits.
1072-1079
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