ITC 1984:
Philadelphia, PA, USA
Proceedings International Test Conference 1984, Philadelphia, PA, USA, October 1984.
IEEE Computer Society 1984 
Session 1: Test Economics
Session 2: Update on Automatic Test Pattern Generation
- Joseph L. A. Hughes, Edward J. McCluskey:
An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets.
52-58
- J. Paul Roth, Vojin G. Oklobdzija, John F. Beetem:
Test Generation for FET Switching Circuits.
59-62
- Brian J. Heard, Ramu N. Sheshadri, Ronald B. David, Arvid G. Sammuli:
Automatic Test Pattern Generation for Asynchronous Networks.
63-69
- Harry H. Chen, Robert G. Mathews, John A. Newkirk:
Test Generation for MOS Circuits.
70-79
- Erwin Trischler:
ATWIG, An Automatic Test Pattern Generator with Inherent Guidance.
80-87
- Tohru Sasaki, Shunichi Kato, Nobuyoshi Nomizu, Hidetoshi Tanaka:
Logic Design Verification Using Automated Test Generation.
88-95
Session 3: New Developments in Test System Accuracy
Session 4: Built-In Self Test Design and Analysis Techniques
Panel Session 5: Implications of Hardware Design Language
- Bulent I. Dervisoglu:
On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification.
184-187
Session 6: Artificial Intelligence in VLSI Test Systems
- A. Jesse Wilkinson:
A Method for Test System Diagnostics Based on the Principles of Artificial Intelligence.
188-195
- Robert Mullis:
An Expert System for VLSI Tester Diagnostics.
196-199
- Gordon D. Robinson:
Artificial Intelligence and Testing.
200-205
Session 7: Printed Circult Board Manufacturing Process and Test Data Management
- Brian C. Crosby:
Adapting CAE Design Information for In-Circuit Test Generation.
206-211
- Graeme R. Kinsey:
Information and Material Flow Within a Production Test Cell.
212-217
Session 8: Recent Developments in Computer Alded Testing
Session 9: Memory Test
Session 10: Stimulus Generation and Application for Built-In-Self Test
Session 11: Intergrated Circult Manufacturing Process and Test Data Management
Session 12: Physical Tralt Measurement on Components
Session 13: Analog and Hybrid Testing
- E. A. Sloane:
Transfer Function Estimation Part I : Theoretical and Practical Considerations.
426-439
- James F. Campbell Jr.:
Transfer Function Estimation Part II : Some Experimental Results.
440-446
- Douglas K. Shirachi:
CODEC Testing Using Synchronized Analog and Digital Signals.
447-454
- Terence Lee:
In-Circuit Analog Component Testing at High Frequencies.
455-461
Session 14: New Directions for VLSI Test Systems
Session 15: Systems Test
Session 16: How, Where, Why, and When of Lsi Burn-In
Session 17: Advanced Probing Techniques for VLSI Devices
- Francois J. Henley:
An Automated Laser Prober to Determine VLSI Internal Node Logic States.
536-542
- Y. Goto, K. Ozaki, T. Ishizuka, A. Ito, Y. Furukawa, T. Inagaki:
Electron Beam Prober for LSI Testing with 100ps Time Resolution.
543-549
- P. Küollensperger, A. Krupp, M. Sturm, R. Weyl, F. Widulla, F. Wolfgang:
Automated Electron Beam Testing of VLSI Circuits.
550-557
Session 18: Advances In Board Test Techniques
Session 19: Software For Successful Test Systems
Session 20: VLSI Microprocessor Testing I
Session 21: Testability Analysis
Session 22: Test Program Generation Tools
Session 24: VLSI Microprocessor Testing II
Session 25: Design for Testability
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