ISSS 2002: Kyoto, Japan
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan. IEEE Computer Society 2002
Processor-Based System
- M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha: A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. 2-7
- Frank Vahid, Susan Cotterell: Tuning of Loop Cache Architectures to Programs in Embedded System Design. 8-13
- Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu: Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors. 14-19
- Daniel Gajski, Junyu Peng: Optimal Message-Passing for Data Coherency in Distributed Architecture. 20-25
- Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli: Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. 26-31
- Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin: An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. 32-37
Reconfigurable System
- Guido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano: Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. 38-43
- Carles Rodoreda Sala, Natalino G. Busá: A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor. 44-49
- Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn: Controller Estimation for FPGA Target Architectures during High-Level Synthesis. 56-61
Practical Experiences
- Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul: System-Level Modeling of a Network Switch SoC. 62-67
- Erwin A. de Kock: Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study. 68-73
- Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto: System-Level Design of IEEE1394 Bus Segment Bridge. 74-79
- Catherine H. Gebotys: Security-Driven Exploration of Cryptography in DSP Cores. 80-85
- Ingo Sander, Axel Jantsch, Zhonghai Lu: A Case Study of Hardware and Software Synthesis in ForSyDe. 86-91
Special Session on On-Chip Multi-Processing
- Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm: An Adaptive Low-Power Transmission Scheme for On-Chip Networks. 92-100
- Shuichi Sakai: CMP on SoC: Architect's View. 101-102
- Satoshi Matsushita: Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification. 103-108
- Mitsuhisa Sato: OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip Multiprocessors. 109-111
Invited Talk
- Rudy Lauwereins, Chun Wong, Paul Marchal, Johan Vounckx, Patrick David, Stefaan Himpe, Francky Catthoor, Peng Yang: Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems. 112-119
Design Methedologies Based on Instruction Code
- Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi: A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design . 120-125
- Abhik Roychoudhury, Xianfeng Li, Tulika Mitra: Timing Analysis of Embedded Software for Speculative Processors. 126-131
- William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame: Modeling Assembly Instruction Timing in Superscalar Architectures. 132-137
- Haris Lekatsas, Wayne Wolf, Yuan Xie: Code Compression for VLIW Processors Using Variable-to-Fixed Coding. 138-143
- Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge: Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops. 144-149
Simulation and Verification
- Petru Eles, Zebo Peng, Daniel Karlsson: Formal Verification in a Component-Based Reuse Methodology. 156-161
- Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu: Validation in a Component-Based Design Flow for Multicore SoCs. 162-167
- Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu: Efficient Simulation of Synthesis-Oriented System Level Designs. 168-173
- Soonhoi Ha, Sungchan Kim, Chan-Eun Rhee, Hyunguk Jung, Youngmin Yi, Dohyung Kim: Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task Graphs. 174-179
- M. Balakrishnan, Anshul Kumar, C. P. Joshi: A New Performance Evaluation Approach for System Level Design Space Exploration. 180-185
- Jürgen Ruf, Thomas Kropf, Jochen Klose: A Visual Approach to Validating System Level Designs. 186-191
Special Session on Security on SoC
- Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys: Special Session: Security on SoC. 192-194
- Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi: Securing Wireless Data: System Architecture Challenges. 195-200
Low Power Memory System
- Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao: Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. 201-206
- Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka: Efficient Power Reduction Techniques for Time Multiplexed Address Buses. 207-212
- M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke: Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. 213-218
- Alex Orailoglu, Peter Petrov: Low-Power Data Memory Communication for Application-Specific Embedded Processors. 219-224
- Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy: System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. 225-230
High Level and Architectural Synthesis
- Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi: A Symbolic Approach for the Combined Solution of Scheduling and Allocation. 237-242
- Vincent John Mooney III, George F. Riley, Eung S. Shin: Round-Robin Arbiter Design and Generation. 243-248
- Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu: An Object-Oriented Design Process for System-on-Chip Using UML. 249-254
- Juan Carlos López, Fernando Rincón, Francisco Moya, José Manuel Moya: Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors. 255-260
- Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta: Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis. 261-266
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last updated on 2013-06-19T201401 by the dblp team