ISSS 1997: Antwerp, Belgium

10th International Symposium on System Synthesis, ISSS '97, September 17-19, 1997, Antwerp, Belgium. IEEE Computer Society, 1997, online publication: http://computer.org/proceedings/isss/7949/7949toc.htm

Formal Specification and Validation

Ellen Sentovich:
Quick Conservative Causality Analysis. 2-8
Christian Blumenröhr, Dirk Eisenbiegler:
An Efficient Representation for Formal Synthesis. 9-15
Steven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin:
Derivation of Formal Representations from Process-Based Specification and Implementation Models. 16-

Fast Prototyping and Code Generation

A. Hein, J. Dalcolmo, P. Le Corre, Rudy Lauwereins, Marleen Adé:
Prototyping of the Receiver Unit for a Broadband Access Network. 26-32
Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
Constraint Analysis for DSP Code Generation. 33-40
Catherine H. Gebotys:
An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy. 41-

Novel Compilation and Optimization Issues

Krzysztof Kuchcinski:
Embedded System Synthesis by Timing Constraints Solving. 50-57
Anne Mignotte, Olivier Peyran:
Reducing the Complexity of ILP Formulations for Synthesis. 58-64
Birger Landwehr, Peter Marwedel:
A New Optimization Technique for Improving Resource Exploitation and Critical Path Minimization. 65-

Memory Management Issues

Peter Slock, Sven Wuytack, Francky Catthoor, Gjalt G. de Jong:
Fast and Extensive System-Level Memory Exploration for ATM Applications. 74-81
Uwe Eckhardt, Renate Merker:
Optimization of the Background Memory Utilization by Partitioning. 82-89
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Architectural Exploration and Optimization of Local Memory in Embedded Systems. 90-

System-Level Synthesis and Design

Robert Pasko, Patrick Schaumont, Veerle Derudder, Daniela Durackova:
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination. 100-106
Frank Vahid:
Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning. 107-112
Smita Bakshi, Daniel Gajski:
A Scheduling and Pipelining Algorithm for Hardware/Software Systems. 113-

HW/SW Specification and Debugging

Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel:
Co-Emulation and Debugging of HW/SW-Systems. 120-125
Henning Dierks:
Synthesising Controllers from Real-Time Specifications. 126-133
Chih-Tung Chen, Kayhan Küçükçakar:
A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis. 134-140

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