Paper Sessions

Plenary Session

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  Anantha Chandrakasan, Hideto Hidaka: Session 1 overview: Plenary session. 7-9
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  Eli Harari: Flash memory - The great disruptor! 10-15
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  Carmelo Papa: The role of semiconductors in the energy landscape. 16-21
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  Yoichi Yano: Take the expressway to go greener. 24-30
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  David Perlmutter: Sustainability in silicon and systems development. 31-35

High-Bandwidth DRAM & PRAM

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  Joo Sun Choi, Daisaburo Takashima: Session 2 overview: High-bandwidth DRAM & PRAM: Memory subcommittee. 36-37
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  Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung-Hwan Choi, Byung-Chul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh: A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. 38-40
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  Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yongju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim: A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. 40-41
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  Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong: A 1.2V 23nm 6F² 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. 42-44
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  Yong-Cheol Bae, Joon-Young Park, Sang Jae Rhee, Seung Bum Ko, Yonggwon Jeong, Kwang-Sook Noh, Younghoon Son, Jaeyoun Youn, Yonggyu Chu, Hyunyoon Cho, Mijo Kim, Daesik Yim, Hyo-Chang Kim, Sang-Hoon Jung, Hye-In Choi, Sungmin Yim, Jung-Bae Lee, Joo-Sun Choi, Kyungseok Oh: A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. 44-46
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  Youngdon Choi, Ickhyun Song, Mu-Hui Park, Hoeju Chung, Sanghoan Chang, Beakhyoung Cho, Jinyoung Kim, Younghoon Oh, Dukmin Kwon, Jung Sunwoo, Junho Shin, Yoohwan Rho, Changsoo Lee, Min Gu Kang, Jaeyun Lee, Yongjin Kwon, Soehee Kim, Jaewhan Kim, Yong-jun Lee, Qi Wang, Sooho Cha, Sujin Ahn, Hideki Horii, Jaewook Lee, KiSeung Kim, Han-Sung Joo, KwangJin Lee, Yeong-Taek Lee, Jei-Hwan Yoo, Gitae Jeong: A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth. 46-48
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  Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim: A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. 48-50
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  Yanghyo Kim, Gyungsu Byun, Adrian Tang, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang: An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. 50-52
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  Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda: A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. 52-54

Processors

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  Joshua Friedrich, Jinuk Luke Shin: Session 3 overview: Processors: High performance digital subcommittee. 54-55
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  Satish Damaraju, George Varghese, Sanjeev Jahagirdar, Tanveer Khondker, Robert Milstrey, Sanjib Sarkar, Scott Siers, Israel Stolero, Arun Subbiah: A 22nm IA multi-CPU and GPU System-on-Chip. 56-57
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  Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain: A 32-core RISC microprocessor with network accelerators, power management and testability features. 58-60
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  Jinuk Luke Shin, Heechoul Park, Hongping Li, Alan Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert Masleid, Georgios Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister: The next-generation 64b SPARC core in a T4 SoC processor. 60-62
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  Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy: 32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. 62-64
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  Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng: An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. 64-66
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  Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar: A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. 66-68
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  Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger: Resonant clock design for a power-efficient high-volume x86-64 microprocessor. 68-70
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  Y. William Li, Carlos Ornelas, Hyung Seok Kim, Hasnain Lakdawala, Ashoke Ravi, Krishnamurthy Soumyanath: A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. 70-72
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  Masoud Zargari, Songcheol Hong: Session 4 overview: RF techniques: RF subcommittee. 72-73

RF Techniques

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  David Murphy, Amr Hafez, Ahmad Mirzaei, Mohyee Mikhemar, Hooman Darabi, Mau-Chung Frank Chang, Asad A. Abidi: A blocker-tolerant wideband noise-cancelling receiver with a 2dB noise figure. 74-76
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  Amir Ghaffari, Eric A. M. Klumperink, Bram Nauta: 8-Path tunable RF notch filters for blocker suppression. 76-78
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  Wei Cheng, Mark S. Oude Alink, Anne-Johan Annema, Gerard Wienk, Bram Nauta: A wideband IM3 cancellation technique for CMOS attenuators. 78-80
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  Seyed Kasra Garakoui, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet: A 1-to-2.5GHz phased-array IC based on gm-RC all-pass time-delay cells. 80-82
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  Bonhoon Koo, Taehwan Joo, Yoosam Na, Songcheol Hong: A fully integrated dual-mode CMOS power amplifier for WCDMA applications. 82-84
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  Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka: A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier. 84-86
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  Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura: A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets. 86-88
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  Ioannis Sarkas, Andreea Balteanu, Eric Dacquay, Alexander Tomkins, Sorin P. Voinigescu: A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing. 88-90

Audio and Power Converters

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  Wing-Hung Ki, Jed Hurwitz: Session 5 overview: Audio and power converters: Analog subcommittee. 90-91
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  Angelo Nagari, Emmanuel Allier, Francois Amiard, Vincent Binet, Christian Fraisse: An 8Ω 2.5W 1%-THD 104dB(A)-dynamic-range Class-D audio amplifier with an ultra-low EMI system and current sensing for speaker protection. 92-94
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  Bert Serneels, Eldert Geukens, Bram De Muer, Tim Piessens: A 1.5W 10V-output Class-D amplifier using a boosted supply from a single 3.3V input in standard 1.8V/3.3V 0.18μm CMOS. 94-96
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  Sunwoo Kwon, Injeong Kim, Shinyoung Yi, Sangheyub Kang, Sangheon Lee, Taeho Hwang, Byoungkwon Moon, Yunyoung Choi, Hosung Sung, Jinseok Koh: A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-end. 96-98
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  Gerard Villar Pique: A 41-phase switched-capacitor power converter with 3.8mV output ripple and 81% efficiency in baseline 90nm CMOS. 98-100
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  Jason Stauth, Michael D. Seeman, Kapil Kesarwani: A high-voltage CMOS IC and embedded system for distributed photovoltaic energy optimization with over 99% effective conversion efficiency and insertion loss below 0.1%. 100-102
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  Reinhard Enne, Miodrag Nikolic, Horst Zimmermann: A maximum power-point tracker without digital signal processing in 0.35μm CMOS for automotive applications. 102-104
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  Jong-Pil Im, Se-Won Wang, Kang-Ho Lee, Young-Jin Woo, Young-sub Yuk, Tae-Hwang Kong, Sung-Wan Hong, Seung-Tak Ryu, Gyu-Hyeong Cho: A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting. 104-106
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  Karthik Kadirvel, Yogesh K. Ramadass, Umar Lyles, John Carpenter, Vadim Ivanov, Vince McNeil, Anantha Chandrakasan, Brian Lum-Shue-Chan: A 330nA energy-harvesting charger with battery management for solar and thermoelectric energy harvesting. 106-108

Medical, Displays and Imagers

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  Yusuke Oike, Maysam Ghovanloo: Session 6 overview: Medical, displays and imagers: Imagers, MEMS, medical and displays subcommittee. 108-109
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  Hyunsik Kim, Sang-Wook Han, Junhyeok Yang, Sung-il Kim, Young Kim, Sangwook Kim, Dae-Kun Yoon, Jun Su Lee, Jae-Chul Park, Younghun Sung, Seong-Deok Lee, Seung-Tak Ryu, Gyu-Hyeong Cho: A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel. 110-112
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  Jaehyuk Choi, Seokjun Park, Jihyun Cho, Euisik Yoon: A 1.36μW adaptive CMOS image sensor with reconfigurable modes of operation from available energy/illumination for distributed wireless sensor network. 112-114
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  Meng-Ting Chung, Chih-Cheng Hsieh: A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise. 114-116
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  Ki-Duk Kim, San-Ho Byun, Yoon-Kyung Choi, Jong-Hak Baek, Hwa-Hyun Cho, Jong-Kang Park, Hae-Yong Ahn, Chang-Ju Lee, Min-Soo Cho, Joo-Hyeon Lee, Sang-Woo Kim, Hyung-Dal Kwon, Yong-Yeob Choi, Hosuk Na, Junchul Park, Yeon-Joong Shin, Kyungsuk Jang, Gyoocheol Hwang, Myunghee Lee: A capacitive touch controller robust to display noise for ultrathin touch screen displays. 116-117
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  Nick Van Helleputte, Sunyoung Kim, Hyejung Kim, Jong Pal Kim, Chris Van Hoof, Refet Firat Yazicioglu: A 160μA biopotential acquisition ASIC with fully integrated IA and motion-artifact suppression. 118-120
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  Kang-Ho Lee, Sukhwan Choi, Jeong Oen Lee, Jun-Bo Yoon, Gyu-Hyeong Cho: CMOS capacitive biosensor with enhanced sensitivity for label-free DNA detection. 120-122
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  David Tyndall, Bruce Rae, David Day-Uei Li, Justin A. Richardson, Jochen Arlt, Robert K. Henderson: A 100Mphoton/s time-resolved mini-silicon photomultiplier with on-chip fluorescence lifetime estimation in 0.13μm CMOS imaging technology. 122-124
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  Hangue Park, Benoit Gosselin, Mehdi Kiani, Hyung-Min Lee, Jeonghee Kim, Xueliang Huo, Maysam Ghovanloo: A wireless magnetoresistive sensing system for an intra-oral tongue-computer interface. 124-126
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  Simone Gambini, Karl Skucha, Paul Peng Liu, Jungkyu Kim, Reut Krigel, Richard Mathies, Bernhard E. Boser: A CMOS 10kpixel baseline-free magnetic bead detector with column-parallel readout for miniaturized immunoassays. 126-128

Multi Gb/s Receiver and Parallel I/O Techniques

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  Robert Payne, Tatsuya Saito: Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommittee. 128-129
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  Meisam Honarvar Nazari, Azita Emami-Neyestanak: An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication. 130-131
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  Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Murugan, Wendemagegnehu T. Beyene, Ken Chang, Chuck Yuan: A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration. 132-134
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  Ankur Agrawal, John F. Bulzacchelli, Timothy O. Dickson, Yong Liu, José A. Tierno, Daniel J. Friedman: A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. 134-136
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  Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, Jae-Yoon Sim: An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. 136-138
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  Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan: A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link. 138-140
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  Seon-Kyoo Lee, Hyunsoo Ha, Hong-June Park, Jae-Yoon Sim: A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation. 140-142
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  Yong Liu, Wing Luk, Daniel J. Friedman: A compact low-power 3D I/O in 45nm CMOS. 142-144

Delta-Sigma Converters

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  Brian Brandt, Gerhard Mitteregger: Session 8 overview: Delta-sigma converters: Data converters subcommittee. 144-145
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  Jeffrey Harrison, Michal Nesselroth, Robert Mamuad, Arya Behzad, Andrew Adams, Steve Avery: An LC bandpass ΔΣ ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs. 146-148
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  Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael Flynn: A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. 148-150
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  Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai: A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW. 150-152
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  Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu: A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. 152-154
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  Pascal Witte, John G. Kauffman, Joachim Becker, Yiannos Manoli, Maurits Ortmanns: A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW. 154-156
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  Pradeep Shettigar, Shanthi Pavan: A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS. 156-158
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  Venkatesh Srinivasan, Victoria Wang, Patrick Satarzadeh, Baher Haroun, Marco Corsi: A 20mW 61dB SNDR (60MHz BW) 1b 3^rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS. 158-160

Wireless Transceiver Techniques

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  Sven Mattisson, Shouhei Kousai: Session 9 overview: Wireless transceiver techniques: Wireless subcommittee. 160-161
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  Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Sam Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello: A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS. 162-164
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  Omid Oliaei, Mark Kirschenmann, David Newman, Kurt Hausmann, Haolu Xie, Patrick Rakers, Mahib Rahman, Michael Gomez, Chuanzhao Yu, Benjamin Gilsdorf, Kurt Sakamoto: A multiband multimode transmitter without driver amplifier. 164-166
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  Shadi Youssef, Ronan A. R. van der Zee, Bram Nauta: Active feedback receiver with integrated tunable RF channel selectivity, distortion cancelling, 48dB stopband rejection and >+12dBm wideband IIP3, occupying ² in 65nm CMOS. 166-168
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  Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas: A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS. 168-170
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  Dixian Zhao, Shailesh Kulkarni, Patrick Reynaert: A 60GHz outphasing transmitter in 40nm CMOS with 15.6dBm output power. 170-172
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  Yuan-Hung Chung, Min Chen, Wei-Kai Hong, Jie-Wei Lai, Sheng-Jau Wong, Chien-Wei Kuan, Hong-Lin Chu, Chihun Lee, Chih-Fan Liao, Hsuan-Yu Liu, Hong-Kai Hsu, Li-Chun Ko, Kuo-Hao Chen, Chao-Hsin Lu, Tsung-Ming Chen, YuLi Hsueh, Chunwei Chang, Yi-Hsien Cho, Chih-Hsien Shen, Yuan Sun, Eng-Chuan Low, Xudong Jiang, Deyong Hu, Weimin Shu, Jhy-Rong Chen, Jui-Lin Hsu, Chia-Jui Hsu, Jing-Hong Conan Zhan, Osama Shana'a, Guang-Kaai Dehng, George Chien: A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS. 172-174
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  Michiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet: A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS. 174-176

High-Performance Digital

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  Lew Chua-Eoan, Se-Hyun Yang: Session 10 overview: High-performance digital: High performance digital subcommittee. 176-177
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  Steven Hsu, Amit Agarwal, Mark Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy: A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS. 178-180
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  Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter, Gerhard Fettweis: A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. 180-182
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  Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar: A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. 182-184
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  Farhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar: A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. 184-186
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  Matt Wordeman, Joel Silberman, Gary Maier, Michael Scheuermann: A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias. 186-187
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  Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim: 3D-MAPS: 3D Massively parallel processor with stacked memory. 188-190
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  David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David Blaauw: Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. 190-192
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  Hiroyuki Miyazaki, Yoshihiro Kusano, Hiroshi Okano, Tatsumi Nakada, Ken Seki, Toshiyuki Shimizu, Naoki Shinjo, Fumiyoshi Shoji, Atsuya Uno, Motoyoshi Kurokawa: K computer: 8.162 PetaFLOPS massively parallel scalar supercomputer built with over 548k cores. 192-194

Sensors & MEMs

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  Christoph Hagleitner, Maurits Ortmanns: Session 11 overview: Sensors and MEMS: Imagers, MEMS, medical and displays subcommittee. 194-195
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  Pedram Lajevardi, Vladimir P. Petkov, Boris Murmann: A ΔΣ interface for MEMS accelerometers using electrostatic spring-constant modulation for cancellation of bondwire capacitance drift. 196-198
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  Sha Xia, Kofi A. A. Makinwa, Stoyan Nihtianov: A capacitance-to-digital converter for displacement sensing with 17b resolution and 20μs conversion time. 198-200
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  Jeroen van den Boom: A 50μW biasing feedback loop with 6ms settling time for a MEMS microphone with digital output. 200-202
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  Marko Rocznik, Fabian Henrici, Remigius Has: ASIC for a resonant wireless pressure-sensing system for harsh environments achieving ±2% error between -40 and 150°C using Q-based temperature compensation. 202-204
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  Caspar P. L. van Vroonhoven, Dan d'Aquino, Kofi A. A. Makinwa: A ±0.4°C (3σ) -70 to 200°C time-domain temperature sensor based on heat diffusion in Si and SiO2. 204-206
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  Michael H. Perrott, Jim Salvia, Fred S. Lee, Aaron Partridge, Shouvik Mukherjee, Carl Arft, Jin-Tae Kim, Niveditha Arumugam, Pavan Gupta, Sassan Tabatabaei, Sudhakar Pamarti, Haechang Lee, Fari Assaderaghi: A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability. 206-208
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  Kamran Souri, Youngcheol Chae, Kofi A. A. Makinwa: A CMOS temperature sensor with a voltage-calibrated inaccuracy of ±0.15°C (3σ) from -55 to 125°C. 208-210
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  Joseph Shor, Kosta Luria, Dror Zilberman: Ratiometric BJT-based thermal sensor in 32nm and 22nm technologies. 210-212

Multimedia & Communications SoCs

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  Byeong-Gyu Nam, Shannon Morton: Session 12 overview: Multimedia and communications SoCs: Energy-efficient digital subcommittee. 212-213
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  Se-Hyun Yang, Seogjun Lee, Jae Young Lee, Jeonglae Cho, Hoi-Jin Lee, Dongsik Cho, Junghun Heo, Sunghoon Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, Seung Ho Hwang: A 32nm high-k metal gate application processor with GHz multi-core CPU. 214-216
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  Markus Winter, Steffen Kunze, Esther P. Adeva, Björn Mennenga, Emil Matús, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, Sebastian Höppner, Stefan Scholze, René Schüffny, Tomoyoshi Kobori: A 335Mb/s 3.9mm² 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. 216-218
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  Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa: A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. 218-220
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  Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Hoi-Jun Yoo: A 320mW 342GOPS real-time moving object recognition processor for HD 720p video streams. 220-222
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  Yasuki Tanabe, Masato Sumiyoshi, Manabu Nishiyama, Itaru Yamazaki, Shinsuke Fujii, Katsuyuki Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori: A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. 222-223
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  Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto: A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. 224-226
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  Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir Mody, Ratna Reddy, Joseph Meehan, Hideo Tamama, Brian Carlson, Mike Polley: A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. 226-228

High-Performance Embedded SRAM

• 
  Leland Chang, Michael Clinton: Session 13 overview: High-performance embedded SRAM: Memory subcommittee. 228-229
• 
  Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr: A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. 230-232
• 
  Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi: A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy. 232-234
• 
  Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James Tschanz, Vivek De: Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. 234-236
• 
  Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki: A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. 236-238

Digital Clocking & PLLs

• 
  Anthony Hill, Hiroo Hayashi: Session 14 overview: Digital clocking and PLLs: High-performance digital subcommittee. 238-239
• 
  Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Tae-Kwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park: A 0.004mm² 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm² 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. 240-242
• 
  Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu: A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. 242-244
• 
  Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen: A 6.7MHz-to-1.24GHz 0.0318mm² fast-locking all-digital DLL in 90nm CMOS. 244-246
• 
  Nathaniel August, Hyung-Jin Lee, Martin Vandepas, Rachael Parker: A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS. 246-248
• 
  Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura: A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS. 248-250

mm-Wave & THz Techniques

• 
  Ehsan Afshari, Yorgos Palaskas: Session 15 overview: Mm-Wave and THz techniques: RF subcommittee. 250-251
• 
  Hani Sherry, Janus Grzyb, Yan Zhao, Richard Al Hadi, Andreia Cathelin, Andreas Kaiser, Ullrich R. Pfeiffer: A 1kpixel CMOS camera chip for 25fps real-time terahertz imaging applications. 252-254
• 
  Ruonan Han, Yaming Zhang, Youngwan Kim, Dae Yeon Kim, Hisashi Shichijo, Ehsan Afshari, K. O. Kenneth: 280GHz and 860GHz image sensors using Schottky-barrier diodes in 0.13μm digital CMOS. 254-256
• 
  Kaushik Sengupta, Ali Hajimiri: A 0.28THz 4×4 power-generation and beam-steering array. 256-258
• 
  Yahya M. Tousi, Omeed Momeni, Ehsan Afshari: A 283-to-296GHz VCO with 0.76mW peak output power in 65nm CMOS. 258-260
• 
  Kun-Yin Wang, Tao-Yao Chang, Chorng-Kuang Wang: A 1V 19.3dBm 79GHz power amplifier in 65nm CMOS. 260-262
• 
  Yong Wang, Wang Ling Goh, Yong-Zhong Xiong: A 9% power efficiency 121-to-137GHz phase-controlled push-push frequency quadrupler in 0.13μm SiGe BiCMOS. 262-264
• 
  Adrian Tang, Gabriel Virbila, David Murphy, Frank Hsiao, Yen-Hsiang Wang, Qun Jane Gu, Zhiwei Xu, Y. Wu, M. Zhu, Mau-Chung Frank Chang: A 144GHz 0.76cm-resolution sub-carrier SAR phase radar for 3D imaging in 65nm CMOS. 264-266
• 
  Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa: A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication. 266-268
• 
  Vojkan Vidojkovic, Giovanni Mangraviti, Khaled Khalaf, Viki Szortyka, Kristof Vaesen, Wim Van Thillo, Bertrand Parvais, Mike Libois, Steven Thijs, John R. Long, Charlotte Soens, Piet Wambacq: A low-power 57-to-66GHz transceiver in 40nm LP CMOS with -17dB EVM at 7Gb/s. 268-270
• 
  Liang Wu, Alvin Li, Howard C. Luong: A 4-path 42.8-to-49.5GHz LO generation with automatic phase tuning for 60GHz phased-array receivers. 270-272

Switching Power Control Techniques

• 
  Baher Haroun, Gyu-Hyeong Cho: Session 16 overview: Switching power control techniques: Analog subcommittee. 272-273
• 
  Chien-Wei Kuan, Hung-Chih Lin: Near-independently regulated 5-output single-inductor DC-DC buck converter delivering 1.2W/mm² in 65nm CMOS. 274-276
• 
  Se-Won Wang, Gyu-Ha Cho, Gyu-Hyeong Cho: A high-stability emulated absolute current hysteretic control single-inductor 5-output switching DC-DC converter with energy sharing and balancing. 276-278
• 
  Jong Tae Hwang, Moon Sang Jung, Dae Ho Kim, Jun Hong Lee, Minho Jung, Jong-Shin Ha: Off-the-line primary-side regulation LED lamp driver with single-stage PFC and TRIAC dimming using LED forward-voltage and duty-variation tracking control. 278-280
• 
  Piero Malcovati, Massimiliano Belloni, Fabio Gozzini, Cristiano Bazzani, Andrea Baschirotto: A 0.18μm CMOS 91%-efficiency 0.1-to-2A scalable buck-boost DC-DC converter for LED drivers. 280-282
• 
  Vincent Ng, Seth Sanders: A 92%-efficiency wide-input-voltage-range switched-capacitor DC-DC converter. 282-284
• 
  Karl Norling, Christian Lindholm, Dieter Draxelmayr: An optimized driver for SiC JFET-based switches delivering more than 99% efficiency. 284-286
• 
  Hyung-Min Lee, Maysam Ghovanloo: An adaptive reconfigurable active voltage doubler/rectifier for extended-range inductive power transmission. 286-288
• 
  Ryota Shinoda, Kazutoshi Tomita, Yuya Hasegawa, Hiroki Ishikuro: Voltage-boosting wireless power delivery system with fast load tracker by ΔΣ-modulated sub-harmonic resonant switching. 288-290

Diagnostic & Therapeutic Technologies for Health

• 
  Alison Burdett, Fu-Lung Hsueh: Session 17 overview: Diagnostic and therapeutic technologies for health: Technology directions subcommittee. 290-291
• 
  Jerald Yoo, Long Yan, Dina El-Damak, Muhammad Bin Altaf, Ali H. Shoeb, Hoi-Jun Yoo, Anantha Chandrakasan: An 8-channel scalable EEG acquisition SoC with fully integrated patient-specific seizure classification and recording processor. 292-294
• 
  Taehwan Roh, Sunjoo Hong, Hyunwoo Cho, Hoi-Jun Yoo: A 259.6μW nonlinear HRV-EEG chaos processor with body channel communication interface for mental health monitoring. 294-296
• 
  Kiseok Song, Hyungwoo Lee, Sunjoo Hong, Hyunwoo Cho, Hoi-Jun Yoo: A sub-10nA DC-balanced adaptive stimulator IC with multimodal sensor for compact electro-acupuncture system. 296-298
• 
  Fan Zhang, Yanqing Zhang, Jason Silver, Yousef Shakhsheer, Manohar Nagaraju, Alicia Klinefelter, Jagdish Nayayan Pandey, James Boley, Eric J. Carlson, Aatmesh Shrivastava, Brian P. Otis, Benton H. Calhoun: A batteryless 19μW MICS/ISM-band energy harvesting body area sensor node SoC. 298-300
• 
  Alan Wong, Mark Dawkins, Gabriele Devita, Nick Kasparidis, Andreas G. Katsiamis, Oliver King, Franco Lauria, Johannes Schiff, Alison Burdett: A 1V 5mA multimode IEEE 802.15.6/bluetooth low-energy WBAN transceiver for biotelemetry applications. 300-302
• 
  Anatoly Yakovlev, Daniel Pivonka, Teresa H. Meng, Ada S. Y. Poon: A mm-sized wirelessly powered and remotely controlled locomotive implantable device. 302-304
• 
  Kang-Ho Lee, Jeonghun Nam, Sukhwan Choi, Hyunjung Lim, Sehyun Shin, Gyu-Hyeong Cho: A CMOS impedance cytometer for 3D flowing single-cell real-time analysis with ΔΣ error correction. 304-306

Innovative Circuits in Emerging Technologies

• 
  Masaitsu Nakajima, Shekhar Borkar: Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee. 306-307
• 
  Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai: Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. 308-310
• 
  Hagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans: 1D and 2D analog 1.5kHz air-stable organic capacitive touch sensors on plastic foil. 310-312
• 
  Kris Myny, Maarten Rockele, Adrian Chasin, Duy-Vu Pham, Jürgen Steiger, Silviu Botnaras, Dennis Weber, Bernhard Herold, Jürgen Ficker, Bas van der Putten, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans: Bidirectional communication in an HF hybrid organic/solution-processed metal-oxide RFID tag. 312-314
• 
  Daniele Raiteri, Fabrizio Torricelli, Kris Myny, Manoj Nag, Bas van der Putten, Edsger Smits, Soeren Steudel, Karin Tempelaars, Ashutosh Tripathi, Gerwin H. Gelinck, Arthur H. M. van Roermund, Eugenio Cantatore: A 6b 10MS/s current-steering DAC manufactured with amorphous Gallium-Indium-Zinc-Oxide TFTs achieving SFDR > 30dB up to 300kHz. 314-316
• 
  Adrian Tang, Frank Hsiao, David Murphy, I.-Ning Ku, Jenny Yi-Chun Liu, Sandeep D'Souza, Ning-Yi Wang, Hao Wu, Yen-Hsiang Wang, Mandy Tang, Gabriel Virbila, Mike Pham, Derek Yang, Qun Jane Gu, Yi-Cheng Wu, Yen-Cheng Kuan, Charles Chien, Mau-Chung Frank Chang: A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip. 316-318
• 
  Violeta Petrescu, Julia Pettine, Devrez M. Karabacak, Marianne Vandecasteele, Mercedes Crego Calama, Chris Van Hoof: Power-efficient readout circuit for miniaturized electronic nose. 318-320
• 
  Gregory Arndt, Cecilia Dupre, Julien Arcamone, Gerald Cibrario, Olivier Rozeau, Laurent Duraffourg, Eric Ollier, Éric Colinet: Towards ultra-dense arrays of VHF NEMS with FDSOI-CMOS active pixels for sensing applications. 320-322

20+Gb/s Wireline Transceivers & Injection-Locked Clocking

• 
  Ken Chang, SeongHwan Cho: Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee. 322-323
• 
  John F. Bulzacchelli, Troy J. Beukema, Daniel Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman: A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. 324-326
• 
  Mike Harwood, Steffen Nielsen, Andre Szczepanek, Richard Allred, Sean Batty, Mike Case, Simon Forey, Karthik Gopalakrishnan, Larry Kan, Bob Killips, Parmanand Mishra, Rohit Pande, Hamid Rategh, Alan Ren, Jeff Sanders, Albrecht Schoy, Richard Ward, Martin Wetterhorn, Norman Yeung: A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications. 326-327
• 
  Diego E. Crivelli, Mario Rafael Hueda, Hugo S. Carrer, Jeff Zachan, Vadim Gutnik, Martin Del Barco, Ramiro Lopez, Geoff Hatcher, Jorge M. Finochietto, Michael Yeo, Andre Chartrand, Norman Swenson, Paul Voois, Oscar E. Agazzi: A 40nm CMOS single-chip 50Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channels. 328-330
• 
  Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Tamer Ali, Nick Huang, Wei Zhang, Bo Zhang, Afshin Momtaz, Jun Cao: A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. 330-332
• 
  Yusuke Tanaka, Yasufumi Hino, Yasuhiro Okada, Takahiro Takeda, Sho Ohashi, Hiroyuki Yamagishi, Kenichi Kawasaki, Ali Hajimiri: A versatile multi-modality serial link. 332-334
• 
  Christian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli, Peter Buchmann, Marcel A. Kossel: A 28Gb/s source-series terminated TX in 32nm CMOS SOI. 334-336
• 
  Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho: An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. 336-337
• 
  Yi-Chieh Huang, Shen-Iuan Liu: A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing. 338-340

RF Frequency Generation

• 
  Robert Bogdan Staszewski, Taizo Yamawaki: Session 20 overview: RF frequency generation: RF subcommittee. 340-341
• 
  Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita: A 20Mb/s phase modulator based on a 3.6GHz digital PLL with -36dB EVM at 5mW power. 342-344
• 
  Dongmin Park, SeongHwan Cho: A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS. 344-346
• 
  Frank Opteynde: A 40nm CMOS all-digital fractional-N synthesizer without requiring calibration. 346-347
• 
  Antonio Liscidini, Luca Fanori, Pietro Andreani, Rinaldo Castello: A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers. 348-350
• 
  Akshay Visweswaran, Robert Bogdan Staszewski, John R. Long: A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations. 350-352
• 
  Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas: A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. 352-354
• 
  Luca Fanori, Antonio Liscidini, Pietro Andreani: A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO. 354-356

Analog Techniques

• 
  Jafar Savoj, Chris Mangelsdorf: Session 21 overview: Analog techniques: Analog subcommittee. 356-357
• 
  Milad Darvishi, Ronan A. R. van der Zee, Eric A. M. Klumperink, Bram Nauta: A 0.3-to-1.2GHz tunable 4^th-order switched gm-C bandpass filter with >55dB ultimate rejection and out-of-band IIP3 of +29dBm. 358-360
• 
  Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu: A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4^th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS. 360-362
• 
  Fawzi Houfaf, Mathieu Egot, Andreas Kaiser, Andreia Cathelin, Bram Nauta: A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications. 362-364
• 
  Anne-Johan Annema, George Goksun: A 0.0025mm² bandgap voltage reference for 1.1V supply in standard 0.16μm CMOS. 364-366
• 
  Dongmin Yoon, Dennis Sylvester, David Blaauw: A 5.58nW 32.768kHz DLL-assisted XO for real-time clocks in wireless sensing applications. 366-368
• 
  Zushu Yan, Pui-In Mak, Man-Kay Law, Rui Paulo Martins: A 0.016mm² 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW. 368-370
• 
  Dario Bianchi, Fabio Quaglia, Andrea Mazzanti, Francesco Svelto: A 90Vpp 720MHz GBW linear power amplifier for ultrasound imaging transmitters in BCD6-SOI. 370-372
• 
  Fridolin Michel, Michiel Steyaert: On-chip gain reconfigurable 1.2V 24μW chopping instrumentation amplifier with automatic resistor matching in 0.13μm CMOS. 372-374
• 
  Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa: A capacitively coupled chopper instrumentation amplifier with a ±30V common-mode range, 160dB CMRR and 5μV offset. 374-376
• 
  Christian Birk, Gerard Mora-Puchalt: A 60V capacitive gain 27nV/√Hz 137dB CMRR PGA with ±10V inputs. 376-377

Image Sensors

• 
  David Stoppa, Robert Johansson: Session 22 overview: Image sensors: Imagers, MEMS, medical and displays subcommittee. 378-379
• 
  Masaki Sakakibara, Yusuke Oike, Takafumi Takatsuka, Akihiko Kato, Katsumi Honda, Tadayuki Taura, Takashi Machida, Jun Okuno, Atsuhiro Ando, Taketo Fukuro, Tomohiko Asatsuma, Suzunori Endo, Junpei Yamamoto, Yasuhiro Nakano, Takumi Kaneshige, Ikuhiro Yamamura, Takayuki Ezaki, Teruo Hirayama: An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage. 380-382
• 
  Yasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, Rihito Kuroda, Hideki Mutoh, Ryuta Hirose, Hideki Tominaga, Kenji Takubo, Yasushi Kondo, Shigetoshi Sugawa: A global-shutter CMOS image sensor with readout speed of 1Tpixel/s burst and 780Mpixel/s continuous. 382-384
• 
  Yue Chen, Yang Xu, Youngcheol Chae, Adri Mierop, Xinyang Wang, Albert Theuwissen: A 0.7e^-rms-temporal-readout-noise CMOS image sensor for low-light-level imaging. 384-386
• 
  Yusuke Oike, Abbas El Gamal: A 256×256 CMOS image sensor with ΔΣ-based single-shot compressed sensing. 386-388
• 
  Toshihisa Watabe, Kazuya Kitamura, Takehide Sawamoto, Tomohiko Kosugi, Tomoyuki Akahori, Tetsuya Iida, Keigo Isobe, Takashi Watanabe, Hiroshi Shimamoto, Hiroshi Ohtake, Satoshi Aoyama, Shoji Kawahito, Norifumi Egami: A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs. 388-390
• 
  Jae-Hong Kim, Wun-ki Jung, Seung-hyun Lim, Yu-jin Park, Won-Ho Choi, Yun-jung Kim, Chang-eun Kang, Ji-hun Shin, Kyo-jin Choo, Won-baek Lee, Jin-kyeong Heo, Byung-jo Kim, Se-jun Kim, Min-ho Kwon, Kwi-sung Yoo, Jin-Ho Seo, Seog-heon Ham, Chi-young Choi, Gab-soo Han: A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor. 390-392
• 
  Wonjoo Kim, Yibing Wang, Ilia A. Ovsiannikov, SeungHoon Lee, Yoondong Park, Chilhee Chung, Eric R. Fossum: A 1.5Mpixel RGBZ CMOS image sensor for simultaneous color and range image capture. 392-394
• 
  Lucio Pancheri, Nicola Massari, Matteo Perenzoni, Mattia Malfatti, David Stoppa: A QVGA-range image sensor based on buried-channel demodulator pixels in 0.18μm CMOS with extended dynamic range. 394-396
• 
  Seong-Jin Kim, Byongmin Kang, James D. K. Kim, KeeChang Lee, Chang-Yeong Kim, Kinam Kim: A 1920×1080 3.65μm-pixel 2D/3D image sensor with split and binning pixel structure in 0.11pm standard CMOS. 396-398

Advances in Heterogeneous Integration

• 
  Tadahiro Kuroda, David Ruffieux: Session 23 overview: Advances in heterogeneous integration: Technology directions subcommittee. 398-399
• 
  Noah Sturcken, Eugene J. O'Sullivan, Naigang Wang, Philipp Herget, Bucknell C. Webb, Lubomyr T. Romankiw, Michele Petracca, Ryan Davies, Robert E. Fontana, Gary M. Decad, Ioannis Kymissis, Angel V. Peterchev, Luca P. Carloni, William J. Gallagher, Kenneth L. Shepard: A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm². 400-402
• 
  Yoonmyung Lee, Gyouho Kim, Suyoung Bang, Yejoong Kim, Inhee Lee, Prabal Dutta, Dennis Sylvester, David Blaauw: A modular 1mm³ die-stacked sensing platform with optical communication and multi-modal energy harvesting. 402-404
• 
  Shuichi Nagai, Noboru Negoro, Takeshi Fukuda, Nobuyuki Otsuka, Hiroyuki Sakai, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda: A DC-isolated gate drive IC with drive-by-microwave technology for power switching devices. 404-406
• 
  Young Yang Liauw, Zhiping Zhang, Wanki Kim, Abbas El Gamal, S. Simon Wong: Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory. 406-408

10GBASE-T & Optical Frontends

• 
  Miki Moyal, Chewnpu Jou: Session 24 overview: 10GBase-T and optical front ends: Wireline subcommittee. 408-409
• 
  Tarun Gupta, Frank Yang, Dong Wang, Ali Tabatabaei, Ramesh Singh, Hesam Amir Aslanzadeh, Alireza Khalili, Saurabh Vats, Susan Arno, Sean Campeau: A sub-2W 10GBase-T analog front-end in 40nm CMOS process. 410-412
• 
  Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani: A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. 412-413
• 
  Hiroshi Koizumi, Minoru Togashi, Masafumi Nogawa, Yusuke Ohtomo: A 10Gb/s burst-mode laser diode driver for burst-by-burst power saving. 414-416
• 
  Xin Yin, Jasmien Put, Jochen Verbrugghe, Jan Gillis, Xing-Zhi Qiu, Johan Bauwelinck, Jan Vandewege, Heinz-Georg Krimmel, Mohand Achouche: A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time. 416-418
• 
  Jonathan Proesel, Clint Schow, Alexander Rylyakov: 25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS. 418-420

Non-Volatile Memory Solutions

• 
  Tadaaki Yamauchi, Satoru Hanzawa: Session 25 overview: Non-volatile memory solutions: Memory subcommittee. 420-421
• 
  Noboru Shibata, Kazushige Kanda, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, K. Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Y. Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, M. Miakashi, Naoki Kobayashi, M. Inagaki, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, D. He, Yasuhiko Honda, Junji Musha, M. Nakagawa, Mitsuaki Honma, Naofumi Abiko, Mitsumasa Koyanagi, M. Yoshihara, Kazumi Ino, Mitsuhiro Noguchi, Teruhiko Kamei, Yosuke Kato, Shingo Zaitsu, Hiroaki Nasu, T. Ariki, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita, G. Liang, Gertjan Hemink, Farookh Moogat, Cuong Trinh, Masaaki Higashitani, Tuan Pham, K. Kanazawa: A 19nm 112.8mm² 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. 422-424
• 
  Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi: Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. 424-426
• 
  Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park: 6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers. 426-428
• 
  Mihail Jefremow, Thomas Kern, Ulrich Backhausen, Christian Peters, Christoph Parzinger, Christoph Roll, Stephan Kassenetter, Stefanie Thierold, Doris Schmitt-Landsiedel: Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive. 428-430
• 
  Daeyeal Lee, Ik Joon Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun: A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. 430-432
• 
  Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Kouhei Tanabe, Toshihiro Nakamura, Yoshihiko Sumimoto, Naoki Yamada, Nobuyuki Nakai, Shoji Sakamoto, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Ken-ichi Origasa, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono: An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput. 432-434
• 
  Meng-Fan Chang, Che-Wei Wu, Chia-Chen Kuo, Shin-Jang Shen, Ku-Feng Lin, Shu-Meng Yang, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih: A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. 434-436
• 
  Yan Li, Seungpil Lee, Ken Oowada, Hao Nguyen, Qui Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, Teruhiko Kamei, Masaaki Higashitani, Tuan Pham, Mitsuaki Honma, Yoshihisa Watanabe, Kazumi Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, Frank Tsai, Kwang-ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, Alex Chu, Chen Chen, Ruchi Puri, Hung-Szu Lin, Yi-Fang Chen, William Mak, Jonathan Huynh, Jim Chan, Mitsuyuki Watanabe, Daniel Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, Tenugu Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, James Lan, Emilio Yero, Feng Pan, Patrick Hong, Jang Yong Kang, Farookh Moogat, Yupin Fong, Raul Cernea, Sharon Huynh, Cuong Trinh, Mehrdad Mofidi, Ritu Shrivastava, Khandker Quader: 128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode. 436-437

Short-Range Wireless Transceivers

• 
  Ranjit Gharpurey, Woogeun Rhee: Session 26 overview: Short-range wireless transceivers: Wireless subcommittee. 438-439
• 
  Masahisa Tamura, Fumitaka Kondo, Katsumi Watanabe, Yasunori Aoki, Yusuke Shinohe, Koki Uchino, Yuhei Hashimoto, Fumihiro Nishiyama, Hiroaki Miyachi, Ikuho Nagase, Itaru Uezono, Rie Hisamura, Itaru Maekawa: A 1V 357Mb/s-throughput transferjet™ SoC with embedded transceiver and digital baseband in 90nm CMOS. 440-442
• 
  Takayuki Abe, Yuxiang Yuan, Hiroki Ishikuro, Tadahiro Kuroda: A 2Gb/s 150mW UWB direct-conversion coherent transceiver with IQ-switching carrier recovery scheme. 442-444
• 
  Lei Wang, Yongxin Guo, Yong Lian, Chun-Huat Heng: 3-to-5GHz 4-channel UWB beamforming transmitter with 1° phase resolution through calibrated vernier delay line in 0.13μm CMOS. 444-446
• 
  Jeongki Choi, Kanghyuk Lee, Seok-Oh Yun, Sang-Gug Lee, Jinho Ko: An interference-aware 5.8GHz wake-up radio for ETCS. 446-448
• 
  Yao-Hong Liu, Xiongchuan Huang, Maja Vidojkovic, Koji Imamura, Pieter Harpe, Guido Dolmans, Harmke de Groot: A 2.7nJ/b multi-standard 2.3/2.4GHz polar transmitter for wireless sensor networks. 448-450
• 
  Xiaoyan Wang, Yikun Yu, Benjamin Busze, Hans Pflug, Alex Young, Xiongchuan Huang, Cui Zhou, Mario Konijnenburg, Kathleen Philips, Harmke de Groot: A meter-range UWB transceiver chipset for around-the-head audio streaming. 450-452
• 
  Giuseppe Papotto, Francesco Carrara, Alessandro Finocchiaro, Giuseppe Palmisano: A 90nm CMOS 5Mb/s crystal-less RF transceiver for RF-powered WSN nodes. 452-454
• 
  Xiongchuan Huang, Ao Ba, Pieter Harpe, Guido Dolmans, Harmke de Groot, John Long: A 915MHz 120μW-RX/900μW-TX envelope-detection transceiver with 20dB in-band interference tolerance. 454-456

Data Converter Techniques

• 
  Dieter Draxelmayr, Takahiro Miki: Session 27 overview: Data converter techniques: Data converters subcommittee. 456-457
• 
  Gil Engel, Shawn Kuo, Steve Rose: A 14b 3/6GHz current-steering RF DAC in 0.18μm CMOS with 66dB ACLR at 2.9GHz. 458-460
• 
  Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon: Ring amplifiers for switched-capacitor circuits. 460-462
• 
  Yun Chai, Jieh-Tsorng Wu: A 5.37mW 10b 200MS/s dual-path pipelined ADC. 462-464
• 
  Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu: A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. 464-466
• 
  Bob Verbruggen, Masao Iriguchi, Jan Craninckx: A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. 466-468
• 
  Jeffrey Fredenburg, Michael P. Flynn: A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC. 468-470
• 
  Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx: A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. 470-472
• 
  Pieter Harpe, Yan Zhang, Guido Dolmans, Kathleen Philips, Harmke de Groot: A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step. 472-474
• 
  Ho-Young Lee, Bumha Lee, Un-Ku Moon: A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS. 474-476

Adaptive & Low-Power Circuits

• 
  Michael Phan, Masaya Sumita: Session 28 overview: Adaptive and low-power circuits: Energy-efficient digital subcommittee. 476-477
• 
  Sudhir Satpathy, Korey Sewell, Thomas Manville, Yen-Po Chen, Ronald G. Dreslinski, Dennis Sylvester, Trevor N. Mudge, David Blaauw: A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS. 478-480
• 
  Chuan-Yung Tsai, Yu-Ju Lee, Chun-Ting Chen, Liang-Gee Chen: A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition. 480-482
• 
  Elio Consoli, Massimo Alioto, Gaetano Palumbo, Jan M. Rabaey: Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS. 482-484
• 
  Sven Lütkemeier, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert: A 200mV 32b subthreshold processor with adaptive supply voltage control. 484-486
• 
  Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. 486-488
• 
  Matthew Fojtik, David Fick, Yejoong Kim, Nathaniel Ross Pinckney, David Money Harris, David Blaauw, Dennis Sylvester: Bubble Razor: An architecture-independent approach to timing-error detection and correction. 488-490
• 
  David Bol, Julien De Vos, Cédric Hocquet, François Botman, François Durvaux, Sarah Boyd, Denis Flandre, Jean-Didier Legat: A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes. 490-492
• 
  Robert Pawlowski, Evgeni Krimer, Joseph Crop, Jacob Postman, Nariman Moezzi Madani, Mattan Erez, Patrick Chiang: A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI. 492-494

Forums

• 
  Eric A. M. Klumperink, Domine Leenaerts, Gabriel M. Rebeiz: Beamforming techniques and RF transceiver design. 498-499
• 
  Ken Takeuchi, Jan Crols, Ken Takeuchi, Jan Crols, Kevin Zhang, Mike Clinton, Tadaaki Yamauchi: Robust VLSI circuit design & systems for sustainable society. 500-501
• 
  Ken Chang, Tony Chan Carusone, Ali Sheikholeslami, Bob Payne, Miki Moyal, John Stonick, Hisakatsu Yamaguchi: 10-40 Gb/s I/O design for data communications. 502-503
• 
  Makoto Ikeda, Albert Theuwissen, Johannes Solhusvik, Jan Bosiers, Makoto Ikeda: Computational imaging. 504-505
• 
  Chris Van Hoof, Wim Dehaene, Wentai Liu, Wim Dehaene, Timothy Denison, Minkyu Je, Wentai Liu, Chris Van Hoof, Hoi-Jun Yoo: Bioelectronics for sustainable healthcare. 506-507
• 
  Stephen Kosonocky, Vladimir Stojanovic, Kees van Berkel, Ming-Yang Chao, Tobias Knoll, Joshua Friedrich: Power/performance optimization of many-core processor SoCs. 508-509

Evening Sessions

• 
  Robert Bogdan Staszewski, Jacques C. Rudell: Is RF doomed to digitization? What shall RF circuit designers do? 510
• 
  Un-ku Moon, Shanthi Pavan: Little-known features of well-known creatures. 511
• 
  Gangadhar Burra, Hossein Hashimi: What is the next RF frontier? 512
• 
  Kazutami Arimoto, Sam Kavusi, Kenneth Salisbury: What's next in robots? ∼Sensing, processing, networking toward human brain and body. 514
• 
  Jed Hurwitz, Jafar Savoj: Technologies that could change the world - You decide! 515
• 
  Ichiro Fujimori, SeongHwan Cho, Joshua Friedrich, John Stonick: Optical PCB interconnects, Niche or mainstream? 516
• 
  Atsuki Inoue, Masaitsu Nakajima: Vision for future television. 517

Short Course

• 
  Willy Sansen, Christian Enz, Willy Sansen, Boris Murmann, Philip K. T. Mok: Low-power analog signal processing. 518

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