ISSCC 2010: San Francisco, CA, USA

Paper Sessions

Plenary Session

• Jiri Marek:
  MEMS for automotive and consumer electronics. 9-17
  
• Greg Delagi:
  Harnessing technology to advance the next-generation mobile user-experience. 18-24
  
• Tomoyuki Suzuki:
  Challenges of image-sensor development. 27-30
  
• James D. Meindl, Azad Naeemi, M. Bakir, R. Murali:
  Nanoelectronics in retrospect, prospect and principle. 31-35
  

mm-Wave Beamforming & RF Building Blocks

• Ta-Shun Chu, Hossein Hashemi:
  A true time-delay-based bandpass multi-beam array at mm-waves supporting instantaneously wide bandwidths. 38-39
  
• Kuba Raczkowski, Walter De Raedt, Bart Nauwelaers, Piet Wambacq:
  A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS. 40-41
  
• Wei L. Chan, John R. Long, Marco Spirito, John J. Pekarik:
  A 60GHz-band 2×2 phased-array transmitter in 65nm CMOS. 42-43
  
• Hua Wang, Constantine Sideris, Ali Hajimiri:
  A 5.2-to-13GHz class-AB CMOS power amplifier with a 25.2dBm peak output power at 21.6% PAE. 44-45
  
• Caroline Andrews, Alyosha C. Molnar:
  A passive-mixer-first receiver with baseband-controlled RF impedance matching, ≪ 6dB NF, and ≫ 27dBm wideband IIP3. 46-47
  
• Luca Fanori, Antonio Liscidini, Rinaldo Castello:
  3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL. 48-49
  
• Salvatore Levantino, Marco Zanuso, Carlo Samori, Andrea L. Lacaita:
  Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band. 50-51
  
• Daniel J. Yeager, Fan Zhang, Azin Zarrasvand, Brian P. Otis:
  A 9.2µA gen 2 compatible UHF RFID sensing tag with -12dBm Sensitivity and 1.25µVrms input-referred noise floor. 52-53
  

Cellular Techniques

• Thomas Dellsperger, David Tschopp, Jürgen Rogin, Yangjian Chen, Thomas Burger, Qiuting Huang:
  A quad-band class-39 RF CMOS receiver for evolved EDGE. 56-57
  
• Jaimin Mehta, Robert B. Staszewski, Oren Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari, Gennady Feygin, Sudheer Vemulapalli, Vasile Zoicas, Chih-Ming Hung, Nathen Barton, Imran Bashir, Kenneth Maggio, Michel Frechette, Meng-Chang Lee, John L. Wallberg, Patrick Cruise, Naveen K. Yanduru:
  A 0.8mm² all-digital SAW-less polar transmitter in 65nm EDGE SoC. 58-59
  
• Qiuting Huang, Jürgen Rogin, Xinhua Chen, David Tschopp, Thomas Burger, Thomas Christen, Dimitris Papadopoulos, Ilian Kouchev, Chiara Martelli, Thomas Dellsperger:
  A tri-band SAW-less WCDMA/HSPA RF CMOS transceiver with on-chip DC-DC converter connectable to battery. 60-61
  
• Xin He, Jan van Sinderen, Robert Rutten:
  A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-end. 62-63
  
• Kimmo Koli, Jarkko Jussila, Pete Sivonen, Sami Kallioinen, Aarno Pärssinen:
  A 900MHz direct ΔΣ receiver in 65nm CMOS. 64-65
  
• Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe:
  A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearization. 66-67
  
• Hyunwon Moon, Sangyoub Lee, Seung-Chan Heo, Hwayeal Yu, Jinhyuck Yu, Ji-Soo Chang, Seung-Il Choi, Byeong-Ha Park:
  A 23mW fully integrated GPS receiver with robust interferer rejection in 65nm CMOS. 68-69
  
• Yiping Feng, Gaku Takemura, Shunji Kawaguchi, Nobuyuki Itoh, Peter R. Kinget:
  A low-power low-noise direct-conversion front-end with digitally assisted IIP2 background self calibration. 70-71
  

Analog Techniques

• Mahdi Kashmiri, Michiel A. P. Pertijs, Kofi A. A. Makinwa:
  A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1% from -55°C to 125°C. 74-75
  
• Massimiliano Belloni, Edoardo Bonizzoni, Andrea Fornasari, Franco Maloberti:
  A micropower chopper-correlated double-sampling amplifier with 2µV standard deviation offset and 37nV/√Hz input noise density. 76-77
  
• Guang Ge, Cheng Zhang, Gian Hoogzaad, Kofi A. A. Makinwa:
  A single-trim CMOS bandgap reference with a 3σ inaccuracy of ±0.15% from -40°C to 125°C. 78-79
  
• Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
  A 21nV/√Hz chopper-stabilized multipath current-feedback instrumentation amplifier with 2µV offset. 80-81
  
• Xicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu:
  A 10mW stereo audio CODEC in 0.13µm CMOS. 82-83
  
• Alex Lollio, Giacomino Bollati, Rinaldo Castello:
  Class-G headphone driver in 65nm CMOS technology. 84-85
  
• Sreekiran Samala, Vineet Mishra, Kalyan Chekuri Chakravarthi:
  45nm CMOS 8Ω Class-D audio driver with 79% efficiency and 100dB SNR. 86-87
  
• Chul Kim, Chang-Seok Chae, Young-sub Yuk, Yi-Gyeong Kim, Jong-Kee Kwon, Gyu-Hyeong Cho:
  A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOS. 88-89
  
• Eoin O'hAnnaidh, Emmanuel Rouat, Sarah Verhaeren, Stéphane Le Tual, Christophe Garnier:
  A 3.2GHz-sample-rate 800mHz bandwidth highly reconfigurable analog FIR filter in 45nm CMOS. 90-91
  
• Vaibhav Maheshwari, Wouter A. Serdijn, John R. Long, John J. Pekarik:
  A 34dB SNDR instantaneously-companding baseband SC filter for 802.11a/g WLAN receivers. 92-93
  

Processors

• Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak, Jeffrey L. Miller, Timothy M. Wilson, Mahadev Nemani, Muntaquim Chowdhury:
  Westmere: A family of 32nm IA processors. 96-97
  
• Jinuk Luke Shin, Kenway Tam, Dawei Huang, Bruce Petrick, Ha Pham, Changku Hwang, Hongping Li, Alan Smith, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong:
  A 40nm 16-core 128-thread CMT SPARC SoC processor. 98-99
  
• Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, S. Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
  A 45nm 37.3GOPS/W heterogeneous multi-core SoC. 100-101
  
• Dieter F. Wendel, Ronald N. Kalla, Robert Cargnoni, Joachim G. Clabes, Joshua Friedrich, R. Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, Victor V. Zyuban:
  The implementation of POWER7^TM: A highly parallel and scalable multi-core high-end server processor. 102-103
  
• Charles L. Johnson, David H. Allen, Jeffrey D. Brown, Steve Vanderwiel, Russ Hoover, Heather D. Achilles, Chen-Yong Cher, George A. May, Hubertus Franke, Jimi Xenedis, Claude Basso:
  A wire-speed power^TM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads. 104-105
  
• Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Greg Constant, A. Novak, Sam Naffziger:
  An x86-64 core implemented in 32nm SOI CMOS. 106-107
  
• Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson:
  A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. 108-109
  
• Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar:
  A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. 110-111
  

Displays & Biomedical Devices

• Hyoung-Rae Kim, Yoon-Kyung Choi, San-Ho Byun, Sang-Woo Kim, Kwang-Ho Choi, Hae-Yong Ahn, Jong-Kang Park, Dong-Yul Lee, Zhong-Yuan Wu, Hyung-Dal Kwon, Yong-Yeob Choi, Chang-Ju Lee, Hwa-Hyun Cho, Jae-Suk Yu, Myunghee Lee:
  A mobile-display-driver IC embedding a capacitive-touch-screen controller system. 114-115
  
• Seok-in Hong, Jin-Wook Han, Dong-Hee Kim, Oh-Kyong Kwon:
  A double-loop control LED backlight driver IC for medium-sized LCDs. 116-117
  
• G. Reza Chaji, Stefan Alexander, J. Marcel Dionne, Yaser Azizi, Corbin Church, John Hamer, Jeff Spindler, Arokia Nathan:
  Stable RGBW AMOLED display with OLED degradation compensation using electrical feedback. 118-119
  
• Seung Bae Lee, Hyung-Min Lee, Mehdi Kiani, Uei-Ming Jow, Maysam Ghovanloo:
  An inductively powered scalable 32-channel wireless neural recording system-on-a-chip for neuroscience applications. 120-121
  
• Zhiming Xiao, Chun-Ming Tang, Christopher M. Dougherty, Rizwan Bashirullah:
  A 20µW neural recording tag with supply-current-modulated AFE in 0.13µm CMOS. 122-123
  
• Refet Firat Yazicioglu, Sunyoung Kim, Tom Torfs, Patrick Merken, Chris Van Hoof:
  A 30µW Analog Signal Processor ASIC for biomedical signal monitoring. 124-125
  
• Xiaodan Zou, Wen-Sin Liew, Libin Yao, Yong Lian:
  A 1V 22µW 32-channel implantable EEG recording IC. 126-127
  
• K. F. E. Lee:
  A timing controlled AC-DC converter for biomedical implants. 128-129
  
• Arun Manickam, Aaron Chevalier, Mark McDermott, Andrew D. Ellington, Arjang Hassibi:
  A CMOS electrochemical impedance spectroscopy biosensor array for label-free biomolecular detection. 130-131
  

Designing in Emerging Technologies

• Wei Xiong, Ute Zschieschang, Hagen Klauk, Boris Murmann:
  A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glass. 134-135
  
• Hagen Marien, Michiel Steyaert, Nick A. J. M. van Aerle, Paul Heremans:
  An analog organic first-order CT ΔΣ ADC on a flexible plastic substrate with 26.5dB precision. 136-137
  
• Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
  User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects. 138-139
  
• Kris Myny, Monique J. Beenhakkers, Nick A. J. M. van Aerle, Gerwin H. Gelinck, Jan Genoe, Wim Dehaene, Paul Heremans:
  Robust digital design in organic electronics by dual-gate technology. 140-141
  
• David D. He, Ivan Nausieda, Kyungbum Kevin Ryu, Akintunde Ibitayo Akinwande, Vladimir Bulovic, Charles Sodini:
  An integrated organic circuit array for flexible large-area temperature sensing. 142-143
  
• Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai:
  Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing. 144-145
  
• Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki:
  A wafer-level heterogeneous technology integration for flexible pseudo-SoC. 146-147
  
• Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne:
  Design issues and considerations for low-cost 3D TSV IC technology. 148-149
  
• Fred Chen, Matthew Spencer, Rhesa Nathanael, Chengcheng Wang, Hossein Fariborzi, Abhinav Gupta, Hei Kam, Vincent Pott, Jaeseok Jeon, Tsu-Jae King Liu, Dejan Markovic, Vladimir Stojanovic, Elad Alon:
  Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications. 150-151
  
• Ali Khaki-Firooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam Shahidi:
  Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. 152-153
  

High-Speed Wireline Transceivers

• Frank O'Mahony, Joseph T. Kennedy, James E. Jaussi, Ganesh Balamurugan, Mozhgan Mansuri, C. Roberts, Sudip Shekhar, Randy Mooney, Bryan Casper:
  A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS. 156-157
  
• Masum Hossain, Anthony Chan Carusone:
  A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS. 158-159
  
• Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin Schmatz:
  A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. 160-161
  
• Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno:
  A 16Gb/s 1^st-Tap FFE and 3-Tap DFE in 90nm CMOS. 162-163
  
• Massimo Pozzoni, Simone Erba, Davide Sanzogni, Marc Ganzerli, Paolo Viola, Daniele Baldi, Matteo Repossi, Giorgio Spelgatti, Francesco Svelto:
  A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization. 164-165
  
• Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Yasumoto Tomita, Hisakatsu Yamaguchi, Masaya Kibune, Takuji Yamamoto:
  A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS. 166-167
  
• Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh:
  A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. 168-169
  
• Sameh A. Ibrahim, Behzad Razavi:
  A 20Gb/s 40mW equalizer in 90nm CMOS technology. 170-171
  

Digital Circuits & Sensors

• Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar:
  Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. 174-175
  
• Ting Wu, Farshid Aryanfar, Hae-Chang Lee, Jie Shen, T. J. Chin, Carl Werner, Ken Chang:
  Low-skew clock distribution using zero-phase-clock-buffer DLLs. 176-177
  
• James D. Warnock, Leon J. Sigal, Dieter F. Wendel, K. Paul Muller, Joshua Friedrich, Victor V. Zyuban, Ethan H. Cannon, A. J. KleinOsowski:
  POWER7^TM local clocking and clocked storage elements. 178-179
  
• Cheolmin Park, Roy Badeau, Larry Biro, Jonathan Chang, Tejpal Singh, Jim Vash, Bo Wang, Tom Wang:
  A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor. 180-181
  
• Jae-sun Seo, Ron Ho, Jon Lexau, Michael Dayringer, Dennis Sylvester, David Blaauw:
  High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS. 182-183
  
• Sherif T. Eid, Morgan Whately, Sandeep Krishnegowda:
  A microcontroller-based PVT control system for a 65nm 72Mb synchronous SRAM. 184-185
  
• Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy:
  Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit. 186-187
  
• David Fick, Nurrachman Liu, Zhiyoong Foo, Matthew Fojtik, Jae-sun Seo, Dennis Sylvester, David Blaauw:
  In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter. 188-189
  
• Prashant Singh, Zhiyoong Foo, Michael Wieckowski, Scott Hanson, Matthew Fojtik, David Blaauw, Dennis Sylvester:
  Early detection of oxide breakdown through in situ degradation sensing. 190-191
  
• Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno:
  A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. 192-193
  

DC-DC Power Conversion

• Ying Wu, Philip K. T. Mok:
  A two-phase switching hybrid supply modulator for polar transmitters with 9% efficiency improvement. 196-197
  
• Eric G. Soenen, Alan Roth, Justin Shi, Martin Kinyua, Justin Gaither, Elizabeth Ortynska:
  A robust digital DC-DC converter with rail-to-rail output range in 40nm CMOS. 198-199
  
• Kwang-Chan Lee, Chang-Seok Chae, Gyu-Ha Cho, Gyu-Hyeong Cho:
  A PLL-based high-stability single-inductor 6-channel output DC-DC buck converter. 200-201
  
• Hani H. Ahmad, Bertan Bakkaloglu:
  A 300mA 14mV-ripple digitally controlled buck converter using frequency domain ΔΣ ADC and hybrid PWM generator. 202-203
  
• Chen Zheng, Dongsheng Ma:
  A 10MHz 92.1%-efficiency green-mode automatic reconfigurable switching converter with adaptively compensated single-bound hysteresis control. 204-205
  
• Pengfei Li, Lin Xue, Deepak Bhatia, Rizwan Bashirullah:
  Digitally assisted discontinuous conduction mode 5V/100MHz and 10V/45MHz DC-DC boost converters with integrated Schottky diodes in standard 0.13µm CMOS. 206-207
  
• Yogesh K. Ramadass, Ayman A. Fayed, Baher Haroun, Anantha Chandrakasan:
  A 0.16mm² completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS. 208-209
  
• Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon:
  A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm² at 81% efficiency. 210-211
  

Radar, mm-Wave, & Low-Power Transceivers

• Harish Krishnaswamy, Hossein Hashemi:
  A 4-channel 4-beam 24-to-26GHz spatio-temporal RAKE radar transceiver in 90nm CMOS for vehicular radar applications. 214-215
  
• Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang, Jri Lee:
  A fully integrated 77GHz FMCW radar system in 65nm CMOS. 216-217
  
• Alberto Valdes-Garcia, Sean Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-Yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Brian A. Floyd:
  A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications. 218-219
  
• Federico Vecchi, Stefano Bozzola, Massimo Pozzoni, Davide Guermandi, Enrico Temporiti, Matteo Repossi, Ugo Decanis, Andrea Mazzanti, Francesco Svelto:
  A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators. 220-221
  
• Xiongchuan Huang, Simonetta Rampu, Xiaoyan Wang, Guido Dolmans, Harmke de Groot:
  A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression. 222-223
  
• Salvatore Drago, D. M. W. Leenaerts, Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Bram Nauta:
  A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes. 224-225
  
• Marco Crepaldi, Chen Li, Keith Dronson, Jorge R. Fernandes, Peter R. Kinget:
  An Ultra-Low-Power interference-robust IR-UWB transceiver chipset using self-synchronizing OOK modulation. 226-227
  
• Sanghoon Joo, Wu-Hsin Chen, Tae-Young Choi, Mi-Kyung Oh, Joo-Ho Park, Jae-Young Kim, Byunghoo Jung:
  A fully integrated 802.15.4a IR-UWB Transceiver in 0.13µm CMOS with digital RRC synthesis. 228-229
  
• Yuanjin Zheng, Shengxi Diao, Chyuen-Wei Ang, Yuan Gao, Foo Chung Choong, Zhiming Chen, Xin Liu, Yisheng Wang, Xiaojun Yuan, Chun-Huat Heng:
  A 0.92/5.3nJ/b UWB impulse radio SoC for communication and localization. 230-231
  

Emerging Medical Applications

• Chii-Wann Lin, Hung-Wei Chiu, Mu-Lien Lin, Chi-Heng Chang, I-Hsiu Ho, Po Hsiang Fang, Yi Chin Li, Chang Lun Wang, Yao-Chuan Tsai, Yeong-Ray Wen, Win-Pin Shih, Yao-Joe Yang, Shey-Shi Lu:
  Pain control on demand based on pulsed radio-frequency stimulation of the dorsal root ganglion using a batteryless implantable CMOS SoC. 234-235
  
• Eric Y. Chow, Sudipto Chakraborty, William J. Chappell, Pedro Irazoqui:
  Mixed-signal integrated circuits for self-contained sub-cubic millimeter biomedical implants. 236-237
  
• Kunal Paralikar, Peng Cong, Wesley Santa, David Dinsmoor, Bob Hocken, Gordon Munns, Jon Giftakis, Timothy Denison:
  An implantable 5mW/channel dual-wavelength optogenetic stimulator for therapeutic neuromodulation research. 238-239
  
• Paolo Livi, Flavio Heer, Urs Frey, Douglas J. Bakkum, Andreas Hierlemann:
  Compact voltage and current stimulation buffer for high-density microelectrode arrays. 240-241
  

Frequency & Clock Synthesis

• Michael H. Perrott, Sudhakar Pamarti, Eric G. Hoffman, Fred S. Lee, Shouvik Mukherjee, Cathy Lee, Vadim Tsinker, Sathi Perumal, Benjamin Soto, Niveditha Arumugam, Bruno W. Garlepp:
  A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator. 244-245
  
• Dennis Michael Fischette, Alvin Leng Sun Loke, Michael M. Oshima, Bruce Andrew Doyle, Roland Bakalski, Richard Joseph DeSantis, Anand Thiruvengadam, Charles Lin Wang, Gerry R. Talbot, Emerson S. Fang:
  A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. 246-247
  
• M. Kondou, A. Matsuda, H. Yamazaki, O. Kobayashi:
  A 0.3mm² 90-to-770MHz fractional-N Synthesizer for a digital TV tuner. 248-249
  
• Shayan Farahvash, William Roberts, Jake Easter, Rachel Wei, David Stegmeir, Li Jin:
  A low-noise frequency synthesizer for infrastructure applications. 250-251
  
• Olivier Richard, Alexandre Siligaris, Franck Badets, Cedric Dehos, Cedric Dufis, Pierre Busson, Pierre Vincent, Didier Belot, Pascal Urard:
  A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications. 252-253
  

Non-Volatile Memory

• David Halupka, S. Huda, W. Song, Ali Sheikholeslami, K. Tsunoda, C. Yoshida, M. Aoki:
  Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS. 256-257
  
• Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe:
  A 64Mb MRAM with clamped-reference and adequate-reference schemes. 258-259
  
• Christophe J. Chevallier, Chang Hua Siau, Seow Fong Lim, Sri Rama Namala, Misako Matsuoka, Bruce L. Bateman, Darrell Rinerson:
  A 0.13µm 64Mb multi-layered conductive metal-oxide memory. 260-261
  
• Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
  A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. 262-263
  
• Shusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda:
  A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card. 264-265
  
• Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi:
  A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. 266-267
  
• Guido De Sandre, Luca Bettini, Alessandro Pirola, Lionel Marmonier, Marco Pasotti, Massimo Borghi, Paolo Mattavelli, Paola Zuliani, Luca Scotti, Gianfranco Mastracchio, Ferdinando Bedeschi, Roberto Gastaldi, Roberto Bez:
  A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput. 268-269
  
• Corrado Villa, Duane Mills, Gerald Barkley, Hari Giduturi, Stefan Schippers, Daniele Vimercati:
  A 45nm 1Gb 1.8V phase-change memory. 270-271
  

Low-Power Processors & Communication

• Christoph Studer, Christian Benkeser, Sandro Belfanti, Quiting Huang:
  A 390Mb/s 3.57mm² 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS. 274-275
  
• Christian Benkeser, Andreas Bubenhofer, Qiuting Huang:
  A 4.5mW digital baseband receiver for level-A evolved EDGE. 276-277
  
• Fabien Clermidy, Christian Bernard, Romain Lemaire, Jérôme Martin, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet, Norbert Wehn:
  A 477mW NoC-based digital baseband for MIMO 4G SDR. 278-279
  
• Yukikuni Nishida, Kenji Kawai, Keiichi Koike:
  A 2Gb/s network processor with a 24mW IPsec offload for residential gateways. 280-281
  
• James Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
  A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. 282-283
  
• David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David Blaauw:
  A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation. 284-285
  
• Greg Burda, Yesh Kolla, Jim Dieffenderfer, Fadi Hamdan:
  A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file. 286-287
  
• Gregory K. Chen, Matthew Fojtik, Daeyeon Kim, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, Dennis Sylvester, David Blaauw:
  Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells. 288-289
  

High-Performance Data Converters

• Ahmed M. A. Ali, Ahmed Morgan, Christopher Dillon, Greg Patterson, Scott Puckett, Mike Hensley, Russell Stop, Paritosh Bhoraskar, Scott Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed:
  A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration. 292-293
  
• Robert Payne, Marco Corsi, David Smith, Scott Kaylor, Daniel Hsieh:
  A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR. 294-295
  
• Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
  A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. 296-297
  
• Gerry Taylor, Ian Galton:
  A mostly digital variable-rate continuous-time ADC ΔΣ modulator. 298-299
  
• Yen-Chuan Huang, Tai-Cheng Lee:
  A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique. 300-301
  
• Benjamin P. Hershberg, Skyler Weaver, Un-Ku Moon:
  A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp. 302-303
  
• Rahmi Hezar, Lars Risbo, Halil Kiper, Mounir Fares, Baher Haroun, G. Burra, Gabriel Gomez:
  A 110dB SNR and 0.5mW current-steering audio DAC implemented in 45nm CMOS. 304-305
  

Sensors & MEMS

• Jun Yin, Jun Yi, Man Kay Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew Ming-Fai Yuen:
  A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor. 308-309
  
• Kamran Souri, Mahdi Kashmiri, Kofi A. A. Makinwa:
  A CMOS temperature sensor with an energy-efficient zoom ADC and an Inaccuracy of ±0.25°C (3s) from -40°C to 125°C. 310-311
  
• Fabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine Leenaerts, Bram Nauta:
  A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C. 312-313
  
• Caspar P. L. van Vroonhoven, Dan d'Aquino, Kofi A. A. Makinwa:
  A thermal-diffusivity-based temperature sensor with an untrimmed inaccuracy of ±0.2°c (3s) from -55°c to 125°c. 314-315
  
• Zhenning Wang, Richard Lin, Eshel Gordon, Hasnain Lakdawala, L. Richard Carley, Jonathan C. Jensen:
  An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators. 316-317
  
• Hossein Miri Lavasani, Wanling Pan, Brandon Harrington, Reza Abdolvand, Farrokh Ayazi:
  A 76dBΩ 1.7GHz 0.18µm CMOS tunable transimpedance amplifier using broadband current pre-amplifier for high frequency lateral micromechanical oscillators. 318-319
  
• Mikail Yücetas, Jarno Salomaa, Antti Kalanti, Lasse Aaltonen, Kari Halonen:
  A closed-loop SC interface for a ±1.4g accelerometer with 0.33% nonlinearity and 2µg/vHz input noise density. 320-321
  
• Bruce Rae, Jonathan McKendry, Zheng Gong, Erdan Gu, David Renshaw, Martin D. Dawson, Robert K. Henderson:
  A 200MHz 300ps 0.5pJ/ns optical pulse generator array in 0.35µm CMOS. 322-323
  

Power-Efficient Media Processing

• Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki:
  A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. 326-327
  
• Amit Agarwal, Sanu Mathew, Steven Hsu, Mark Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar:
  A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. 328-329
  
• Tzu-Der Chuang, Pei-Kuei Tsung, Pin-Chih Lin, Lo-Mei Chang, Tsung-Chuan Ma, Yi-Hau Chen, Liang-Gee Chen:
  A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications. 330-331
  
• Seungjin Lee, Jinwook Oh, Minsu Kim, Junyoung Park, Joonsoo Kwon, Hoi-Jun Yoo:
  A 345mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition. 332-333
  
• Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto:
  A scalable massively parallel processor for real-time image processing. 334-335
  
• Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim:
  A graphics and vision unified processor with 0.89µW/fps pose estimation engine for augmented reality. 336-337
  
• Tse-Wei Chen, Yi-Ling Chen, Teng-Yuan Cheng, Chi-Sun Tang, Pei-Kuei Tsung, Tzu-Der Chuang, Liang-Gee Chen, Shao-Yi Chien:
  A multimedia semantic analysis SoC (SASoC) with machine-learning engine. 338-339
  

High-Performance Embedded Memory

• John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael Sperling, Abraham Mathews, William R. Reohr, Kavita Nair, N. Cao:
  A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache. 342-343
  
• Jürgen Pille, Dieter F. Wendel, Otto Wagner, Rolf Sautter, Wolfgang Penth, Thomas Fröhnel, Stefan Büttner, Otto A. Torreiter, Martin Eckert, Jose Paredes, David Hrusecky, David Ray, Miles Canada:
  A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor. 344-345
  
• Hyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang:
  A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. 346-347
  
• Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe:
  A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm² cell in 32nm high-k metal-gate CMOS. 348-349
  
• Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha Chandrakasan:
  A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS. 350-351
  
• Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah:
  PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. 352-353
  
• Jason Tsai, Seng Oon Toh, Zheng Guo, Liang-Teck Pang, Tsu-Jae King Liu, Borivoje Nikolic:
  SRAM stability characterization using tunable ring oscillators in 45nm CMOS. 354-355
  
• Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara:
  A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. 356-357
  

Next-Generation Optical & Electrical Interfaces

• Daniel Kucharski, Drew Guckenberger, Gianlorenzo Masini, Sherif Abdalla, J. Witzens, Subal Sahni:
  10Gb/s 15mW optical receiver with integrated Germanium photodetector and hybrid inductor peaking in 0.13µm SOI CMOS technology. 360-361
  
• Dongmyung Lee, Jung-Won Han, Eunsoo Chang, Gunhee Han, Sung Min Park:
  An 8.5Gb/s CMOS OEIC with on-chip photodiode for short-distance optical communications. 362-363
  
• Kenichi Maruko, Tatsuya Sugioka, Hiroaki Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Yuki Yagishita, Hironobu Konishi, Toshikyuki Ogata, Hisashi Owa, Taichi Niki, Kenji Konda, Masahiro Sato, Hiro Shiroshita, Takeshi Ogura, Takayuki Aoki, Hiroki Kihara, Sachiya Tanaka:
  A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator. 364-365
  
• Fulvio Spagna, Lidong Chen, Mamatha Deshpande, Yongping Fan, Doug Gambetta, Sujatha Gowder, Sitaraman Iyer, Rohit Kumar, Peter Kwok, Renuka Krishnamurthy, Chien-chun Lin, Ravindran Mohanavelu, Roan Nicholson, Jeff Ou, M. Pasquarella, Kavitha Prasad, Hendra Rustam, Luke Tong, Amanda Tran, John Wu, Xuguang Zhang:
  A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS. 366-367
  
• Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Tatsuya Saito:
  A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. 368-369
  
• Wayne D. Dettloff, John C. Eble, Lei Luo, Pravin Kumar, Fred Heaton, Teva Stone, Barry Daly:
  A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI. 370-371
  
• Ganesh Balamurugan, Frank O'Mahony, Mozhgan Mansuri, James E. Jaussi, Joseph T. Kennedy, Bryan Casper:
  A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS. 372-373
  
• Ke-Chung Wu, Jri Lee:
  A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications. 374-375
  

Successive-Approximation ADCs

• Christopher P. Hurrell, Colin Lyden, David Laing, Derek Hummerston, Mark Vickery:
  An 18b 12.5MHz ADC with 93dB SNR. 378-379
  
• Wenbo Liu, Pingli Huang, Yun Chiu:
  A 12b 22.5/45MS/s 3.0mW 0.059mm² CMOS SAR ADC achieving over 90dB SFDR. 380-381
  
• Masanori Furuta, Mai Nozawa, Tetsuro Itakura:
  A 0.06mm² 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS. 382-383
  
• Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto:
  A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration. 384-385
  
• Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang, Chih-Hao Huang, Linkai Bu, Chih-Chung Tsai:
  A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. 386-387
  
• Pieter Harpe, Cui Zhou, Xiaoyan Wang, Guido Dolmans, Harmke de Groot:
  A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS. 388-389
  
• Yuriy M. Greshishchev, Jorge Aguirre, Marinette Besson, Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang:
  A 40GS/s 6b ADC in 65nm CMOS. 390-391
  

Image Sensors

• Youngcheol Chae, Jimin Cheon, Seunghyun Lim, Dongmyung Lee, Minho Kwon, Kwisung Yoo, Wunki Jung, Dong-Hun Lee, Seogheon Ham, Gunhee Han:
  A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture. 394-395
  
• Yong Lim, Kyoungmin Koh, Kyungmin Kim, Han Yang, Juha Kim, Youngkyun Jeong, Seungjin Lee, Hansoo Lee, Sin-Hwan Lim, Yunseok Han, Jinwoo Kim, Jaecheol Yun, Seogheon Ham, Yun-Tae Lee:
  A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling. 396-397
  
• Keita Yasutomi, Shinya Itoh, Shoji Kawahito:
  A 2.7e- temporal noise 99.7% shutter efficiency 92dB dynamic range CMOS image sensor with dual global shutter pixels. 398-399
  
• Christoph Posch, Daniel Matolin, Rainer Wohlgenannt:
  A QVGA 143dB dynamic range asynchronous address-event PWM dynamic image sensor with lossless pixel-level video compression. 400-401
  
• Shinya Itoh, Isamu Takai, M. Shakowat Zaman Sarker, Moeta Hamai, Keita Yasutomi, Michinori Andoh, Shoji Kawahito:
  A CMOS image sensor for 10Mb/s 70m-range LED-based spatial optical communication. 402-403
  
• Shingo Mandai, Makoto Ikeda, Kunihiro Asada:
  A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary. 404-405
  
• David Stoppa, Nicola Massari, Lucio Pancheri, Mattia Malfatti, Matteo Perenzoni, Lorenzo Gonzo:
  An 80×60 range image sensor based on 10µm 50MHz lock-in pixels in 0.18µm CMOS. 406-407
  
• Takeo Azuma, Taro Imagawa, Sanzo Ugawa, Yusuke Okada, Hiroyoshi Komobuchi, Motonori Ishii, Shigetaka Kasuga, Yoshihisa Kato:
  A 2.2/3-inch 4K2K CMOS image sensor based on dual resolution and exposure technique. 408-409
  
• Hayato Wakabayashi, Keiji Yamaguchi, Masafumi Okano, Souichiro Kuramochi, Oichi Kumagai, Seijiro Sakane, Masamichi Ito, Masahiro Hatano, Masaru Kikuchi, Yuuki Yamagata, Takeshi Shikanai, Ken Koseki, Keiji Mabuchi, Yasushi Maruyama, Kentaro Akiyama, Eiji Miyata, Tomoyuki Honda, Masanori Ohashi, Tetsuo Nomoto:
  A 1/2.3-inch 10.3Mpixel 50frame/s Back-Illuminated CMOS image sensor. 410-411
  

mm-Wave Transceivers, Power Amplifiers & Sources

• Kenichi Kawasaki, Yoshiyuki Akiyama, Kenji Komori, Masahiro Uno, Hidenori Takeuchi, Tomoari Itagaki, Yasufumi Hino, Yoshinobu Kawasaki, Katsuhisa Ito, Ali Hajimiri:
  A millimeter-wave intra-connect solution. 414-415
  
• Ullrich R. Pfeiffer, Erik Öjefors, Yan Zhao:
  A SiGe quadrature transmitter and receiver chipset for emerging high-frequency applications at 160GHz. 416-417
  
• Dan Sandström, Mikko Varonen, Mikko Kärkkäinen, Kari Halonen:
  A W-band 65nm CMOS transmitter front-end with 8GHz IF bandwidth and 20dB IR-ratio. 418-419
  
• Amin Arbabian, Bagher Afshar, Jun-Chau Chien, Shinwon Kang, Steven Callender, Ehsan Adabi, Stefano Dal Toso, Romain Pilard, Daniel Gloria, Ali M. Niknejad:
  A 90GHz-carrier 30GHz-bandwidth hybrid switching transmitter with integrated antenna. 420-421
  
• Andrea Mazzanti, Enrico Monaco, Massimo Pozzoni, Francesco Svelto:
  A 13.1% tuning range 115GHz frequency generator based on an injection-locked frequency doubler in 65nm CMOS. 422-423
  
• Jie-Wei Lai, Alberto Valdes-Garcia:
  A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOS. 424-425
  
• Chi Y. Law, Anh-Vu Pham:
  A high-gain 60GHz power amplifier with 20dBm output power in 90nm CMOS. 426-427
  
• Baudouin Martineau, Vincent Knopik, Alexandre Siligaris, Frederic Gianesello, Didier Belot:
  A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS. 428-429
  
• Erik Öjefors, Ullrich R. Pfeiffer:
  A 650GHz SiGe receiver front-end for terahertz imaging arrays. 430-431
  

DRAM & Flash Memories

• Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun:
  A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. 434-435
  
• Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda:
  An 8Tb/s 1pJ/b 0.8mm²/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM. 436-437
  
• Myoung Jin Lee, Ki Myung Kyung, Hyung Sik Won, Myoung Su Lee, Kun Woo Park:
  A bitline sense amplifier for offset compensation. 438-439
  
• Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda:
  A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking. 440-441
  
• Hyunggon Kim, Jung-hoon Park, Ki-Tae Park, Pansuk Kwak, Ohsuk Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyun Cho, Juseok Lee, Jungho Song, Soowoong Lee, Hyukjun Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, Kyehyun Kyung, Yong-Ho Lim, Chilhee Chung:
  A 159mm² 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface. 442-443
  
• G. G. Marotta, A. Macerola, A. D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, D. Rivers, E. Sirizotti, F. Paolini, G. Imondi, G. Naso, G. Santin, L. Botticchio, L. De Santis, L. Pilolli, M. L. Gallese, M. Incarnati, M. Tiburzi, P. Conenna, S. Perugini, V. Moschiano, W. Di Francesco, Matt Goldman, Chris Haid, D. Di Cicco, D. Orlandi, F. Rori, Massimo Rossini, Tommaso Vali, R. Ghodsi, F. Roohparvar:
  A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s. 444-445
  
• Changhyuk Lee, Sok-Kyu Lee, Sunghoon Ahn, Jinhaeng Lee, Wonsun Park, Yongdeok Cho, Chaekyu Jang, Chulwoo Yang, Sanghwa Chung, In-Suk Yun, Byoungin Joo, Byoungkwan Jeong, Jeeyul Kim, Jeakwan Kwon, Hyunjong Jin, Yujong Noh, Jooyun Ha, Moonsoo Sung, Daeil Choi, Sanghwan Kim, Jeawon Choi, Taeho Jeon, Joong-Seob Yang, Yo-Hwan Koh:
  A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS. 446-447
  

Wireless Connectivity

• Frank Opteynde:
  A maximally-digital radio receiver front-end. 450-451
  
• Ali Afsahi, Arya Behzad, Lawrence E. Larson:
  A 65nm CMOS 2.4GHz 31.5dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applications. 452-453
  
• Chungyeol P. Lee, Arya Behzad, Bojko Marholev, Vikram Magoon, Iqbal Bhatti, Dandan Li, Subhas Bothra, Ali Afsahi, Dayo Ojo, Rozi Roufoogaran, Tom Li, Yuyu Chang, Kishore Rama Rao, Stephen Au, Prasad Seetharam, Keith Carter, Jacob Rael, Malcolm Macintosh, Bobby Lee, Maryam Rofougaran, Reza Rofougaran, Amir Hadji-Abdolhamid, Mohammad Nariman, Shahla Khorram, Seema Anand, Ed Chien, Steve Wu, Carol Barrett, Lijun Zhang, Alireza Zolfaghari, Hooman Darabi, Ali Sarfaraz, Brima Ibrahim, Mark Gonikberg, Marcellus Forbes, Colin Fraser, Luis Gutierrez, Yury Gonikberg, Madjid Hafizi, Siukai Mak, Jesse Castaneda, Kimmer Kim, Zhenhua Liu, Stamatis Bouras, Kevin Chien, Vinay Chandrasekhar, Paul Chang, Edwin Li, Zhimin Zhao:
  A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier. 454-455
  
• Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada:
  A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS. 456-457
  
• Mark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx:
  A 5mm² 40nm LP CMOS 0.1-to-3GHz multistandard transceiver. 458-459
  
• Minsu Jeong, Bonkee Kim, Youngho Cho, Yanggyun Kim, Seyeob Kim, Heeyong Yoo, Junghwan Lee, Jae Kyung Lee, Kyung Soo Jung, Jeiyoung Lee, Junghun Lee, Huikwan Yang, Gerry Taylor, Bo-Eun Kim:
  A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC. 460-461
  
• Jae-Hong Chang, Huijung Kim, Jeong-Hyun Choi, Hangun Chung, Jungwook Heo, Sanghoon Kang, Jong-Dae Bae, Heetae Oh, Youngwoon Kim, Taek-Won Kwon, Ryan Kim, Wooseung Choo, Dojun Rhee, Byeong-ha Park:
  A multistandard multiband mobile TV RF SoC in 65nm CMOS. 462-463
  
• Erwan Le Roux, Nicola Scolari, Budhaditya Banerjee, Claude Arm, Patrick Volet, Daniel Sigg, Pascal Heim, Jean-Félix Perotto, François Kaess, Nicolas Raemy, Alexandre Vouilloz, David Ruffieux, Matteo Contaldo, Frédéric Giroud, Daniel Séverac, Marc Morgan, Steve Gyger, Cedric Monneron, Thanh-Chau Le, Cesar Henzelin, Vincent Peiris:
  A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks. 464-465
  

High-Performance & Digital PLLs

• Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Marco Cusmai, Francesco Svelto:
  A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. 468-469
  
• Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi:
  A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. 470-471
  
• Mike Shuo-Wei Chen, David Su, Srenik Mehta:
  A calibration-free 800MHz fractional-N digital PLL with embedded TDC. 472-473
  
• Xiang Gao, Eric A. M. Klumperink, Gerard Socci, Mounir Bohsali, Bram Nauta:
  Spur-reduction techniques for PLLs using sub-sampling phase detection. 474-475
  
• Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita:
  A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation. 476-477
  
• Werner Grollitsch, Roberto Nonis, Nicola Da Dalt:
  A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. 478-479
  
• Jonathan Borremans, Kameswaran Vengattaramane, Kameswaran Giannini, Jan Craninckx:
  A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS. 480-481
  
• Seon-Kyoo Lee, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
  A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS. 482-483
  

Directions in Health, Energy & RF

• Yogesh K. Ramadass, Anantha P. Chandrakasan:
  A batteryless thermoelectric energy-harvesting interface circuit with 35mV startup voltage. 486-487
  
• Nan Sun, Tae-Jong Yoon, Hakho Lee, William Andress, Vasiliki Demas, Pablo Prado, Pablo Weissleder, Donhee Ham:
  Palm NMR and one-chip NMR. 488-489
  
• Long Yan, Joonsung Bae, Seulki Lee, Binhee Kim, Taehwan Roh, Kiseok Song, Hoi-Jun Yoo:
  A 3.9mW 25-electrode reconfigured thoracic impedance/ECG SoC with body-channel transponder. 490-491
  
• David Garner, Hua Bai, Pantelis Georgiou, Timothy G. Constandinou, Samuel Reed, Leila Shepherd, Winston Wong, K. T. Lim, Christofer Toumazou:
  A multichannel DNA SoC for rapid point-of-care gene detection. 492-493
  
• Dongwon Kwon, Gabriel A. Rincón-Mora:
  A single-inductor AC-DC piezoelectric energy-harvester/battery-charger IC converting ±(0.35 to 1.2V) to (2.7 to 4.5V). 494-495
  
• Patrick P. Mercier, Anantha P. Chandrakasan:
  A 110µW 10Mb/s etextiles transceiver for body area networks with remote battery power. 496-497
  
• Matteo Contaldo, David Ruffieux, Christian C. Enz:
  A 5.4dBm 42mW 2.4GHz CMOS BAW-based quasi-direct conversion transmitter. 498-499
  
• Michael W. Chen, David S. Ricketts:
  An 8.6GHz 42ps pulse-width electrical mode-locked oscillator. 500-501
  
• Travis Kleeburg, Jeffrey Loo, Nathaniel J. Guilar, Erin G. Fong, Rajeevan Amirtharajah:
  Ultra-low-voltage circuits for sensor applications powered by free-space optics. 502-503
  
• Toshishige Shimamura, Mamoru Ugajin, Kenji Suzuki, Kazuyoshi Ono, Norio Sato, Kei Kuwabara, Hiroki Morimura, Shin'ichiro Mutoh:
  Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence applications. 504-505
  

Forums

• Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai:
  Silicon 3D-integration technology and systems. 510-511
  
• Stefan Heinen, Domine Leenaerts, Trudy Stetzler, Yiannos Manoli, Jan Craninckx, Ali Niknejad, Didier Belot, Raf Roovers, K. P. Pun, Jed Hurwitz:
  Reconfigurable RF and data converters. 512-513
  
• Yuriy M. Greshishchev, Franz Dielacher, Michael Flynn, Donhee Ham, Naresh R. Shanbhag, Takuji Yamamoto:
  Transceiver circuits for optical communications. 514-515
  
• Johannes Solhusvik, Jung-Chak Ahn, Jan Bosiers, Boyd Fowler, Makoto Ikeda, Shoji Kawahito, Jerry Lin, Dan McGrath, Katsu Nakamura, Jun Ohta, Ramchan Woo:
  High-speed image sensor technologies. 516-517
  
• Jos Huisken, Alice Wang, Andrea Baschirotto, Alison Burdett, Tim Denison, Maysam Ghovanloo, Jun Ohta, Zhihua Wang:
  Circuits for portable medical electronic systems. 518-519
  
• Don Draper, Fabio Campi, Ram Krishnamurthy, Takashi Miyamori, Shannon Morton, Willy Sansen, Vladimir Stojanovic, John Stonick:
  Signal and power integrity for SoCs. 520
  

Short Course

• Ian Galton, Behzad Razavi, John Cowles, Peter R. Kinget:
  CMOS phase-locked loops for frequency synthesis. 521
  

Evening Sessions

• Donhee Ham, David Scott:
  Beyond CMOS - emerging technologies. 522
  
• Jan Van der Spiegel:
  Student research preview. 523
  
• Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne:
  Energy-efficient high-speed interfaces. 524-525
  
• Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner:
  Fusion of MEMS and circuits. 526-527
  
• Jed Hurwitz, Bill Redman-White, Chris Mangelsdorf:
  Analog circuits: Stump the panel. 528-529
  
• Robert Bogdan Staszewski, Jacques C. Rudell:
  Can RF SoCs (Self)test their own RF? 530-531
  
• Maysam Ghovanloo, Tim Denison:
  Can we rebuild them? bionics beyond 2010. 532-533
  
• Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva Narendra:
  The semiconductor industry in 2025. 534-535
  

Last update Fri May 25 08:24:23 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page