ISQED 2012:
Santa Clara, California, USAKeith A. Bowman , Kamesh V. Gadepally , Pallab Chatterjee , Mark M. Budnik , Lalitha Immaneni (Eds.):
Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012.
IEEE 2012, ISBN 978-1-4673-1034-5 Test and Measurement
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conf/isqed/NelsonSMGWZCWRYW12 Kelvin Nelson ,
Jaga Shanmugavadivelu ,
Jayanth Mekkoth ,
Venkat Ghanta ,
Jun Wu ,
Fei Zhuang ,
Hao-Jan Chao ,
Shianling Wu ,
Jie Rao ,
Lizhen Yu ,
Laung-Terng Wang :
Physical-design-friendly hierarchical logic built-in self-test - A case study.
1-6
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Reliable System Design
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conf/isqed/PoolakkaparambilMJM12 export record as
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System Frameworks and Tools
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Shirish Bahirat ,
Sudeep Pasricha :
A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip.
78-83
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conf/isqed/MagalhaesLFAH12
Thermal and Power in 3D ICs
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Low Power Communication Circuits
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Yongtae Kim ,
Peng Li :
An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration.
151-158
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Karthik Rajagopal :
Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process.
159-164
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Process-Induced Variability & Hot Spot Detection
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conf/isqed/Gower-HallGWTEYBG12 export record as
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Emerging Topics in EDA
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Design & Analysis of Emerging Devices
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Chenyun Pan ,
Azad Naeemi :
Device- and system-level performance modeling for graphene P-N junction logic.
262-269
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conf/isqed/TsukamotoYFNSL12 export record as
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Shaloo Rakheja ,
Azad Naeemi :
Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits.
283-290
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Variation-Aware Design Methodologies
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Haiqing Nan ,
Li Li ,
Ken Choi :
TDDB-based performance variation of combinational logic in deeply scaled CMOS technology.
328-333
Poster Session
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Riadul Islam :
A highly reliable SEU hardened latch and high performance SEU hardened flip-flop.
347-352
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conf/isqed/GurugubelliK12 export record as
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conf/isqed/ShrivastavaP12 export record as
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Bin Wu :
Dynamic range estimation for systems with control-flow structures.
370-377
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Tong Xu ,
Peng Li :
Design and optimization of power gating for DVFS applications.
391-397
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conf/isqed/Abdel-MajeedCA12 export record as
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conf/isqed/AntunesSAFSHM12
Physical Design
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Robust SRAM Design
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conf/isqed/TeradaYOSMKY12 export record as
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conf/isqed/Samandari-RadGH12 export record as
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conf/isqed/KagiyamaOYYNIKY12
3D Effects on Package Co-Design
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conf/isqed/TripathiNCMM12 export record as
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Advanced Analysis & Characterization for Sub-Micron Design
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conf/isqed/GaritselovMKO12
Power-Aware Design
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conf/isqed/YasufukuHPZTSFMNSTS12 Tadashi Yasufuku ,
Koji Hirairi ,
Yu Pu ,
Yun Fei Zheng ,
Ryo Takahashi ,
Masato Sasaki ,
Hiroshi Fuketa ,
Atsushi Muramatsu ,
Masahiro Nomura ,
Hirofumi Shinohara ,
Makoto Takamiya ,
Takayasu Sakurai :
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.
586-591
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Atsuki Inoue :
Comparison between power gating and DVFS from the viewpoint of energy efficiency.
601-608
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conf/isqed/RavishankarAGK12 export record as
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Circuit-Level Variability & Manufacturability
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conf/isqed/Mirza-AghatabarBGN12 export record as
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Rouwaida Kanj ,
Rajiv V. Joshi :
A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability.
672-678
Verification & Silicon Debug
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Mao-Yin Wang ,
Jen-Chieh Yeh :
Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL.
679-685
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conf/isqed/KarputkinUTR12 export record as
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conf/isqed/GharehbaghiF12 export record as
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Challenges & Opportunities in New Technologies
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Shaloo Rakheja ,
Vachan Kumar :
Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations.
732-739
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Energy-Aware System Design
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Hao Shen ,
Jun Lu ,
Qinru Qiu :
Learning based DVFS for simultaneous temperature, performance and energy management.
747-754
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conf/isqed/HomayounRKGT12 export record as
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Mahboobeh Ghorbani :
A variation and energy aware ILP formulation for task scheduling in MPSoC.
772-777
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Keisuke Inoue ,
Mineo Kaneko :
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis.
778-783
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