Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni (Eds.):
Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012.
IEEE 2012, ISBN 978-1-4673-1034-5
Santa Clara, California, USA
Test and Measurement
, Jaga Shanmugavadivelu
, Jayanth Mekkoth
, Venkat Ghanta
, Jun Wu
, Fei Zhuang
, Hao-Jan Chao
, Shianling Wu
, Jie Rao
, Lizhen Yu
, Laung-Terng Wang
: Physical-design-friendly hierarchical logic built-in self-test - A case study.
Reliable System Design
System Frameworks and Tools
, Sudeep Pasricha
: A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip.
Thermal and Power in 3D ICs
Low Power Communication Circuits
, Peng Li
: An ultra-low voltage digitally controlled low-dropout regulator with digital background calibration.
: Dynamically biased low power high performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process.
Process-Induced Variability & Hot Spot Detection
Emerging Topics in EDA
Design & Analysis of Emerging Devices
, Azad Naeemi
: Device- and system-level performance modeling for graphene P-N junction logic.
, Azad Naeemi
: Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits.
Variation-Aware Design Methodologies
, Li Li
, Ken Choi
: TDDB-based performance variation of combinational logic in deeply scaled CMOS technology.
: A highly reliable SEU hardened latch and high performance SEU hardened flip-flop.
: Dynamic range estimation for systems with control-flow structures.
, Peng Li
: Design and optimization of power gating for DVFS applications.
Robust SRAM Design
3D Effects on Package Co-Design
Advanced Analysis & Characterization for Sub-Micron Design
, Koji Hirairi
, Yu Pu
, Yun Fei Zheng
, Ryo Takahashi
, Masato Sasaki
, Hiroshi Fuketa
, Atsushi Muramatsu
, Masahiro Nomura
, Hirofumi Shinohara
, Makoto Takamiya
, Takayasu Sakurai
: 24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.
: Comparison between power gating and DVFS from the viewpoint of energy efficiency.
Circuit-Level Variability & Manufacturability
, Rajiv V. Joshi
: A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability.
Verification & Silicon Debug
Challenges & Opportunities in New Technologies
, Vachan Kumar
: Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations.
Energy-Aware System Design
, Jun Lu
, Qinru Qiu
: Learning based DVFS for simultaneous temperature, performance and energy management.
: A variation and energy aware ILP formulation for task scheduling in MPSoC.
, Mineo Kaneko
: Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis.