ISQED 2011: Santa Clara, California, USA

Device Aging: Analysis and Design

• Saurabh Kothawade, Koushik Chakraborty, Sanghamitra Roy:
  Analysis and mitigation of NBTI aging in register file: An end-to-end approach. 1-7
  
• Shailesh More, Michael Fulde, Florian Chouard, Doris Schmitt-Landsiedel:
  Reducing impact of degradation on analog circuits by chopper stabilization and autozeroing. 8-13
  
• Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang:
  Circuit-level delay modeling considering both TDDB and NBTI. 14-21
  
• Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera:
  Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation. 22-27
  
• Taniya Siddiqua, Sudhanva Gurumurthi, Mircea R. Stan:
  Modeling and analyzing NBTI in the presence of Process Variation. 28-35
  

Analog and 3D Integrated Circuits

• Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai:
  A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. 36-41
  
• Chang Liu, Taigon Song, Sung Kyu Lim:
  Signal integrity analysis and optimization for 3D ICs. 42-49
  
• Cheng-Chi Chan, Yen-Ting Yu, Iris Hui-Ru Jiang:
  3DICE: 3D IC cost evaluation based on fast tier number estimation. 50-55
  
• Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
  Accurate analysis of substrate sensitivity of active transistors in an analog circuit. 56-61
  
• Amir Grinshpon, Adam Segoli Schubert, Ziyang Lu:
  Full-chip analysis of unintentional forward biased diodes. 62-66
  

Low Power Circuits, Sensors, and Memories

• Basab Datta, Wayne Burleson:
  A 12.4μm² 133.4μW 4.56mV/°C resolution digital on-chip thermal sensing circuit in 45nm CMOS utilizing sub-threshold operation. 67-73
  
• Li Li, Ken Choi, Haiqing Nan:
  Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously. 74-79
  
• Kyu-Nam Shim, Jiang Hu:
  Transient and fine-grained voltage adaptation for variation resilience in VLSI interconnects. 80-86
  
• Michael Wieckowski, Gregory K. Chen, Daeyeon Kim, David Blaauw, Dennis Sylvester:
  A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers. 87-90
  
• Nikhil Gupta, Rabi N. Mahapatra:
  Temperature aware energy management for real-time scheduling. 91-96
  

Lithography and 3D Integration

• Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky:
  Coupling timing objectives with optical proximity correction for improved timing yield. 97-102
  
• Minoo Mirsaeedi, J. Andres Torres, Mohab Anis:
  Self-aligned double patterning (SADP) layout decomposition. 103-109
  
• S. M. Stalin, Amit Brahme, Ramakrishnan Venkatraman, Ajoy Mandal:
  DFM: Impact analysis in a high performance design. 110-115
  
• Jen-Yi Wuu, Fedor G. Pikus, Malgorzata Marek-Sadowska:
  Metrics for characterizing machine learning-based hotspot detection methods. 116-121
  
• Taigon Song, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Jonghyun Cho, Joohee Kim, Junso Pak, Seungyoung Ahn, Joungho Kim, Kihyun Yoon:
  Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. 122-128
  
• Ding-Ming Kwai, Chang-Tzu Lin:
  3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement. 129-134
  

New Ideas in Digital Design Automation

• Cary Y. Yang:
  Compact circuit modeling of RF characteristics of 1-D nanostructures. 135
  
• Evriklis Kounalakis, Christos P. Sotiriou:
  SCPlace: A statistical slack-assignment based constructive placer. 136-143
  
• Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto:
  Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. 144-149
  
• Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto:
  Novel and efficient min cut based voltage assignment in gate level. 150-155
  
• Fatemeh Kashfi, Safar Hatami, Massoud Pedram:
  Multi-objective optimization techniques for VLSI circuits. 156-163
  

System Frameworks and Tools

• Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, Jose Renau:
  A design time simulator for computer architects. 164-173
  
• Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo:
  Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. 174-181
  
• Soohyun Kwon, Sudeep Pasricha, Jeonghun Cho:
  POSEIDON: A framework for application-specific Network-on-Chip synthesis for heterogeneous chip multiprocessors. 182-188
  
• Mineo Kaneko:
  A complete framework of simultaneous functional unit and register binding with skew scheduling. 189-195
  
• Alexandra Aguiar, Fabiano Hessel:
  Virtual Hellfire Hypervisor: Extending Hellfire Framework for embedded virtualization support. 129-203
  
• Sudeep Pasricha, Yong Zou:
  A low overhead fault tolerant routing scheme for 3D Networks-on-Chip. 204-211
  

Variation and Noise-Aware Design

• Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty:
  Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors. 212-218
  
• Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi:
  0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. 219-222
  
• Michael B. Healy, Sung Kyu Lim:
  Power-supply-network design in 3D integrated systems. 223-228
  
• Sabyasachi Deyati, Pradip Mandal:
  An automated design methodology for yield aware analog circuit synthesis in submicron technology. 229-235
  
• Ying Teng, Baris Taskin:
  Process variation sensitivity of the Rotary Traveling Wave Oscillator. 236-242
  

Physical Design Issues in Custom Circuits and FPGAs

• Xiaoyu Shi, Dahua Zeng, Yu Hu, Guohui Lin, Osmar R. Zaïane:
  Enhancement of incremental design for FPGAs using circuit similarity. 243-250
  
• Aswin Sreedhar, Sandip Kundu:
  On discovery of "missing" physical design rules via diagnosis of soft-faults. 251-256
  
• Meng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou:
  Mixed non-rectangular block packing for non-Manhattan layout architectures. 257-262
  
• Yiding Han, Sanghamitra Roy, Koushik Chakraborty:
  Optimizing simulated annealing on GPU: A case study with IC floorplanning. 263-269
  
• Nan Liu, Song Chen, Takeshi Yoshimura:
  Floorplanning for high utilization of heterogeneous FPGAs. 270-275
  

Verification, Validation and Test

• Xiaoke Qin, Prabhat Mishra:
  Efficient directed test generation for validation of multicore architectures. 276-283
  
• Amir Masoud Gharehbaghi, Masahiro Fujita:
  Global transaction ordering in Network-on-Chips for post-silicon validation. 284-289
  
• Eddie Hung, Steven J. E. Wilton:
  On evaluating signal selection algorithms for post-silicon debug. 290-296
  
• Bijan Alizadeh, Masahiro Fujita:
  Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques. 297-302
  
• Leyi Yin, Peng Li:
  RF BIST for ADPLL-based polar transmitters with wide-band DCO gain calibration. 303-310
  

Poster Session & Mixer

• Mohamed O. Shaker, Magdy A. Bayoumi:
  A 90 nm low-power successive approximation register for A/D conversions. 311-315
  
• Alireza Hassanzadeh, Robert G. Lindquist:
  A low noise CMOS interface circuit for capacitive liquid crystal chemical and biological sensor. 316-321
  
• Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto:
  Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. 322-325
  
• Daniela De Venuto, Sandro Carrara, Andrea Cavallini, Giovanni De Micheli:
  pH sensing with temperature compensation in a Molecular Biosensor for drugs detection. 326-331
  
• Talal Al-Attar:
  CMOS diodes operating beyond avalanche frequency. 332-337
  
• Sandeep Koranne, John Ferguson, Bikram Garg, Manish Khanna:
  Entropy-reduced hashing for physical IP management. 338-342
  
• Benjamin D. Horwath, Talal Al-Attar:
  A physical model for tunable patch antennas. 343-346
  
• Bo Jiang, Tian Xia:
  Model analysis of multi-finger MOSFET layout in ring oscillator design. 347-352
  
• Tuhina Samanta, Sanoara Khatun, Hafizur Rahaman, Parthasarathi Dasgupta:
  Crosstalk aware coupled line delay tree construction for on-chip interconnects. 353-358
  
• Tsu-Yun Hsueh, Hsiang-Hui Yang, Wei-Chieh Wu, Mely Chen Chi:
  A layer prediction method for minimum cost three dimensional integrated circuits. 359-363
  
• Kumar Yelamarthi, Chien-In Henry Chen:
  Delay optimization considering power saving in dynamic CMOS circuits. 364-369
  
• Anisha Raj Seli, Hoa Nguyen, Lili He, Morris Jones:
  Capacitor free phase locked loop design in 45nm. 370-375
  
• Rance Rodrigues, Sandip Kundu:
  Model based double patterning lithography (DPL) and simulated annealing (SA). 376-383
  
• Shreyas Kumar Krishnappa, Hamid Mahmoodi:
  Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology. 384-389
  
• Changmin Jung, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong:
  Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations. 390-397
  
• Guoyuan Fu, H. Alan Mantooth, Jia Di:
  A 12-bit CMOS current steering D/A converter with a fully differential voltage output. 398-404
  
• Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos:
  Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling. 405-410
  
• Philippe Morey-Chaisemartin, Eric Beisser, Jean-Claude Marin, Lidwine Chaize, Pascal Guyader, Julien Rosa:
  CMP monitoring and prediction based metal fill. 311-416
  
• Qian Ying Tang, Costas J. Spanos:
  Non-Gaussian uncertainty propagation in statistical circuit simulation. 417-424
  
• Randy W. Mann, Benton H. Calhoun:
  New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm. 425-430
  
• Savithri Sundareswaran, Robert L. Maziasz, Vladimir Rozenfeld, Mikhail Sotnikov, Mukhanov Konstantin:
  A sensitivity-aware methodology to improve cell layouts for DFM guidelines. 431-436
  
• Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
  Lithography-aware layout modification considering performance impact. 437-441
  
• José Augusto Miranda Nacif, Thiago S. F. Silva, Luiz Filipe M. Vieira, Alex Borges Vieira, Antônio Otávio Fernandes, Claudionor Coelho:
  Tracking hardware evolution. 442-447
  
• Bogdan Tudor, Joddy Wang, Zhaoping Chen, Robin Tan, Weidong Liu, Frank Lee:
  An accurate and scalable MOSFET aging model for circuit simulation. 448-451
  
• Rasit Onur Topaloglu:
  Fast variational static IR-drop analysis on the graphical processing unit. 452-457
  
• Sandeep Miryala, Baljit Kaur, Bulusu Anand, Sanjeev Manhas:
  Efficient nanoscale VLSI standard cell library characterization using a novel delay model. 458-463
  
• Dheepakkumaran Jayaraman, Spyros Tragoudas:
  Occurrence probability analysis of a path at the architectural level. 464-468
  
• Pinping Sun, Cole Zemke, Wayne H. Woods, Nick Perez, Hailing Wang, Essam Mina, Barbara Dewitt:
  Automatic post-layout flow validation tool for Deep Sub-micron process design kits. 469-472
  
• Srini Krishnamoorthy, Vishak Venkatraman, Yuri Apanovich, Thomas Burd, Anand Daga:
  Switching constraint-driven thermal and reliability analysis of Nanometer designs. 473-480
  
• Jun Ye, QingPing Tan, Tun Li:
  Separation of communication and computation in SystemC/TLM modeling: A Feature-Oriented approach. 481-485
  
• Anirban Sengupta, Reza Sedaghat:
  Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration. 486-494
  
• Hui Zhao, Mahmut T. Kandemir, Mary Jane Irwin:
  Exploring performance-power tradeoffs in providing reliability for NoC-based MPSoCs. 495-501
  
• Sophie Belloeil-Dupuis, Roselyne Chotin-Avot, Habib Mehrez:
  Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. 502-507
  

Variation, Reliability, and Test

• Tarek A. El-Moselhy, Luca Daniel:
  Variation-aware stochastic extraction with large parameter dimensionality: Review and comparison of state of the art intrusive and non-intrusive techniques. 508-517
  
• Adam Neale, Manoj Sachdev:
  Digitally programmable SRAM timing for nano-scale technologies. 518-524
  
• Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake:
  Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. 525-532
  
• Weiwei Pan, Jie Ren, Yongjun Zheng, Zheng Shi, Xiaolang Yan:
  Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test array. 533-538
  
• Karthik Balakrishnan, Keith A. Jenkins, Duane S. Boning:
  A simple array-based test structure for the AC variability characterization of MOSFETs. 539-544
  

Package and Processor Co-Design for Reliability and Signal/Power Integrity

• Joseph Fjelstad:
  Reliability - A highly important product attribute for the world's poorest consumers. 545-547
  
• Raj Kumar Nagpal, Jai Narayan Tripathi, Rakesh Malik:
  Cost-effective optimization of serial link system for Signal Integrity and Power Integrity. 548-552
  
• Sheldon Logan, Matthew R. Guthaus:
  Package-chip co-design to increase flip-chip C4 reliability. 553-558
  
• Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu:
  Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloads. 559-565
  

System Design Considerations

• Shahin Golshan, Love Singhal, Eli Bozorgzadeh:
  Process variation aware system-level load assignment for total energy minimization using stochastic ordering. 566-571
  
• Krishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja:
  A low cost approach to calibrate on-chip thermal sensors. 572-576
  
• Kyungsu Kang, Jongpil Jung, Sungjoo Yoo, Chong-Min Kyung:
  Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory. 577-582
  

Error-Resilient Design

• David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev:
  Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops. 583-590
  
• Mohammad Hossein Neishaburi, Zeljko Zilic:
  ERAVC: Enhanced reliability aware NoC router. 591-596
  
• Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita:
  SEU tolerant SRAM cell. 597-602
  
• Warin Sootkaneung, Kewal K. Saluja:
  Soft error reduction through gate input dependent weighted sizing in combinational circuits. 603-610
  
• Sandeep Sriram, Haiqing Nan, Ken Choi:
  Low power latch design in near sub-threshold region to improve reliability for soft error. 611-614
  
• Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty:
  BCH code based multiple bit error correction in finite field multiplier circuits. 615-620
  

Routing, Signal Integrity, and Timing Closure

• Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao:
  A novel fine-grain track routing approach for routability and crosstalk optimization. 621-626
  
• Chi-Wen Pan, Yu-Min Lee:
  Redundant via insertion under timing constraints. 627-633
  
• Jui-Hung Hung, Yao-Kai Yeh, Yung-Sheng Tseng, Tsai-Ming Hsieh:
  A new ECO technology for functional changes and removing timing violations. 634-638
  
• Bassel Soudan:
  The effect of SRNR on timing characteristics of signal busses. 639-645
  
• Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li:
  Gridless wire ordering, sizing and spacing with critical area minimization. 646-653
  
• Chang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen:
  Clock planning for multi-voltage and multi-mode designs. 654-658
  

Power Delivery and Estimation

• Bosun Hwang, Jongeun Koo, Chanseok Hwang, Younghoi Cheon, Sooyoung Ahn, Jongbae Lee, Moonhyun Yoo:
  Fast power delivery network analyzer. 659-662
  
• Zhiyu Zeng, Zhuo Feng, Peng Li:
  Efficient checking of power delivery integrity for power gating. 663-670
  
• Zhigang Hao, Sheldon X.-D. Tan, Guoyong Shi:
  An efficient statistical chip-level total power estimation method considering process variations with spatial correlation. 671-676
  
• Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai:
  Statistical full-chip dynamic power estimation considering spatial correlations. 677-682
  
• Sudhanshu Khanna, Kyle Craig, Yousef Shakhsheer, Saad Arrabi, John Lach, Benton H. Calhoun:
  Stepped Supply Voltage Switching for energy constrained systems. 683-688
  
• Kyungseok Kim, Vishwani D. Agrawal:
  Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates. 689-694
  

Design Methodologies for CMOS and Beyond

• Ajay N. Bhoj, Niraj K. Jha:
  Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. 695-702
  
• Behnam Ghavami, Mohsen Raji, Hossein Pedram:
  Timing yield estimation of carbon nanotube-based digital circuits in the presence of nanotube density variation and metallic-nanotubes. 703-710
  
• Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal:
  Measuring within-die spatial variation profile through power supply current measurements. 711-715
  
• Tim Tuan, Austin Lesea, Chris Kingsley, Steven Trimberger:
  Analysis of within-die process variation in 65nm FPGAs. 716-720
  
• Yu Ben, Costas J. Spanos:
  Estimating the probability density function of critical path delay via partial least squares dimension reduction. 721-727
  

Advanced Devices and Manufacturing Technologies

• Khawla Alzoubi, Daniel G. Saab, Sijing Han, Massood Tabib-Azar:
  Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling. 728-735
  
• Shaloo Rakheja, Azad Naeemi:
  Interconnection aspects of spin torque devices: Delay, energy-per-bit, and circuit size modeling. 736-744
  
• Soo Youn Kim, Selin Baytok, Kaushik Roy:
  Scaled LTPS TFTs for low-cost low-power applications. 745-750
  
• Nauman H. Khan, Syed M. Alam, Soha Hassoun:
  Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs. 751-756
  
• Rasit Onur Topaloglu:
  Device and circuit implications of double-patterning - A designer's perspective. 757-760
  

New Ideas in Analog Design Automation

• Supriyo Maji, Samiran Dam, Pradip Mandal:
  Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizing. 761-768
  
• Thiago Figueiro, Renato P. Ribas, André Inácio Reis:
  Constructive AIG optimization considering input weights. 769-776
  
• Kuo-Hsuan Meng, Po-Cheng Pan, Hung-Ming Chen:
  Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping. 777-784
  
• Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato:
  A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. 785-790
  
• Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho:
  Multi-mode redundancy removal. 791-799
  

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