Introduction

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  Welcome Notes.
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  Organizing Committee.
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  Technical Subcommittees.
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  Steering/Advisory Committee.
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  Conference at a Glance.

ISQED Tutorials

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  Rajiv V. Joshi, Kaustav Banerjee, André DeHon: Tutorial 1: Emerging Technologies for VLSI Design. 4
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  Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar: Tutorial II: Variability and Its Impact on Design. 5

ISQED Panel Discussion

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  Michael Santarini, Pallab K. Chatterjee: Session EP1: Power Management and Optimization Challenges for Sub 90nm CMOS Designs- What is the Real Cost of Long Battery Life?. 7

ISQED Plenary Session

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  Risto Suoranta: Modular service-oriented platform architecture - a key enabler to SoC design quality. 11-13
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  T. Furuyama: Deep sub-100 nm Design Challenges. 13-14
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  Di Ma: Successful IP Business Models. 15-18

Session 1A: Variation Aware Timing

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  Praveen Ghanta, Sarma B. K. Vrudhula: Variational Interconnect Delay Metrics for Statistical Timing Analysis. 19-24
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  Evelyn Grossar, Michele Stucchi, Karen Maex, Wim Dehaene: Statistically Aware SRAM Memory Array Design. 25-30
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  Zhiyu Liu, Volkan Kursun: Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. 31-36
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  Andrew B. Kahng, Bao Liu, Xu Xu: Constructing Current-Based Gate Models Based on Existing Timing Library. 37-42
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  Zhuo Feng, Peng Li, Jiang Hu: Efficient Model Update for General Link-Insertion Networks. 43-50

Session 1B: High-Level Design Verification

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  Miroslav N. Velev: Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction. 51-56
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  Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli: EFSM Manipulation to Increase High-Level ATPG Effectiveness. 57-62
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  Indradeep Ghosh, Mukul R. Prasad: A Technique for Estimating the Difficulty of a Formal Verification Problem. 63-70
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  Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: A Formal Verification Method of Scheduling in High-level Synthesis. 71-78

Session 1C: Physical Planning

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  Anand Rajaram, David Z. Pan: Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. 79-84
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  Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai: Clock Distribution Architectures: A Comparative Study. 85-91
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  Narender Hanchate, Nagarajan Ranganathan: Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. 92-97
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  Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. 98-104

ISQED Luncheon Speech

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  Michael Keating: Simplicity and Executability: Cornerstones of Quality. 105

Session 2A: Robust Device and Circuit Design

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  Yogesh Singh Chauhan, C. Anghel, François Krummenacher, Renaud Gillon, A. Baguenier: A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor. 109-114
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  Jin He, Xing Zhang, Ganggang Zhang, Mansun Chan, Yangyuan Wang: A Complete Carrier-Based Non-Charge-Sheet Analytic Theory for Nano-Scale Undoped Surrounding-Gate MOSFETs. 115-120
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  Brian Swahn, Soha Hassoun: METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs. 121-126
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  Jin He, Xing Zhang, Ganggang Zhang, Yangyuan Wang: A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs. 127-132
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  Chong Zhao, Sujit Dey: Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO). 133-140

Session 2B: Power, Noise and Timing Issues in DSM Designs

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  Soheil Ghiasi, Po-Kuan Huang: Probabilistic Delay Budgeting for Soft Realtime Applications. 141-146
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  Jindrich Zejda, Li Ding: TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro Blocks. 147-152
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  Nahmsuk Oh, Li Ding, Alireza Kasnavi: Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback Loop. 153-159
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  Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar: Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. 159-164
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  Deniz Dal, Adrian Nunez, Nazanin Mansouri: Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. 165-170
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  Andrew Havlir, David Z. Pan: Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. 171-178

Session 2C: Memory Analysis

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  Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif: System-Level SRAM Yield Enhancement. 179-184
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  Young-Gu Kim, Sang-Hoon Lee, Dae-Han Kim, Jae-Woo Im, Sung-Eun Yu, Dae-Wook Kim, Young-Kwan Park, Jeong-Taek Kong: Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model. 185-189
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  R. Venkatraman, R. Castagnetti, S. Ramesh: The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. 190-195
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  Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto: A Simulation-Based Soft Error Estimation Methodology for Computer Systems. 196-203
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  Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif: SRAM Local Bit Line Access Failure Analyses. 204-209
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  Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar: Impact of NBTI on SRAM Read Stability and Design for Reliability. 210-218

Session 2D: Posters

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  Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas: Minimizing FPGA Reconfiguration Data at Logic Level. 219-224
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  Kaiping Zeng, Sorin A. Huss: Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques. 225-230
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  Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen: Language-Based High Level Transaction Extraction on On-chip Buses. 231-236
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  Xinjie Wei, Yici Cai, Xianlong Hong: Clock Skew Scheduling Under Process Variations. 237-242
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  Qikai Chen, Mesut Meterelliyoz, Kaushik Roy: A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. 243-248
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  Rasit Onur Topaloglu: Monte Carlo-Alternative Probabilistic Simulations for Analog Systems. 249-253
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  Peng Li: Critical Path Analysis Considering Temperature, Power Supply Variations and Temperature Induced Leakage. 254-259
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  C. Tabery, M. Craig, G. Burbach, B. Wagner, S. McGowan, P. Etter, S. Roling, C. Haidinyak, E. Ehrichs: Process Window and Device Variations Evaluation using Array-Based Characterization Circuits. 260-265
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  Xiongfei Meng, Resve A. Saleh, Karim Arabi: Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. 266-271
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  Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong: Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. 272-277
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  Seongkyun Shin, Yungseon Eo: Non-Physical Pseudo-Wave-Based Modal Decoupling Technique of Multi- Coupled Co-Planar Transmission Lines with Homogeneous Dielectric Media. 278-283
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  Krishna Srinivasan, P. Muthana, Rohan Mandrekar, Ege Engin, Jinwoo Choi, Madhavan Swaminathan: Enhancement of Signal Integrity and Power Integrity with Embedded Capacitors in High-Speed Packages. 284-291
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  Cheng Zhuo, Jiang Hu, Kangsheng Chen: An Improved AMG-based Method for Fast Power Grid Analysis. 290-295
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  Miroslav N. Velev: Formal Verification of Pipelined Microprocessors with Delayed Branches. 296-299
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  Arkan Abdulrahman, Spyros Tragoudas: Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level. 300-305
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  Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Random Variables. 306-311
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  Ali Bastani, Charles A. Zukowski: A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology. 312-317
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  Zhiyu Liu, Volkan Kursun: Leakage Biased Sleep Switch Domino Logic. 318-323
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  Randy Bach, Bob Davis, Rich Laubhan: Improvements to CBCM (Charge-Based Capacitance Measurement) for Deep Submicron CMOS Technology. 324-329
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  Sajid Baloch, Tughrul Arslan, Adrian Stoica: Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices. 330-345
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  Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys: Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects. 334-339
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  Jia Wang, Hai Zhou, Ping-Chih Wu: Processing Rate Optimization by Sequential System Floorplanning. 340-345
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  Zile Wei, Donald Chai, A. Richard Newton, Andreas Kuehlmann: Fast Boolean Matching with Don't Cares. 346-351
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  Krishnan Srinivasan, Karam S. Chatha: A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. 352-357
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  Praveen Bhojwani, Rabi N. Mahapatra: Core Network Interface Architecture and Latency Constrained On-Chip Communication. 358-363
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  Vyas Krishnan, Srinivas Katkoori: Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation. 364-369
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  Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita: Equivalence Checking of C Programs by Locally Performing Symbolic Simulation on Dependence Graphs. 370-375
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  Concepción Sanz, Manuel Prieto, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor: System-level process variability compensation on memory organizations of dynamic applications: a case study. 376-382
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  Biye Wang, Lili He, Morris Jones: A low input, low-power dissipation CMOS ADC. 383-386
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  J. Balachandran, Steven Brebels, Geert Carchon, Walter De Raedt, Eric Beyne, Maarten Kuijk, Bart Nauwelaers: Constant Impedance Scaling Paradigm for Scaling LC transmission lines. 387-392
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  Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai: Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. 393-400

Session 3A: Interconnect Analysis and Optimization

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  Min Chen, Yu Cao: Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design. 401-406
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  Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra: Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk. 407-412
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  Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu: Compact Reduced Order Modeling for Multiple-Port Interconnects. 413-418
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  Taeyong Je, Yungseon Eo: Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching. 419-424
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  Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De: Reducing the Data Switching Activity on Serial Link Buses. 425-432

Session 3B: Digital Test and Diagnosis Techniques

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  Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos: Efficient Multiphase Test Set Embedding for Scan-based Testing. 433-438
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  Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael: Evaluation of Collapsing Methods for Fault Diagnosis. 439-444
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  Yu Huang: On N-Detect Pattern Set Optimization. 445-450
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  Li-Chung Hsu, Hung-Ming Chen: On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. 451-456
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  Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas: An Improved Method for Identifying Linear Dependencies in Path Delay Faults. 457-462
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  Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski: Delay Fault Diagnosis for Non-Robust Test. 463-472

Session 3C: Back of Line DFM

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  Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte: Yield Improvement by Local Wiring Redundancy. 473-478
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  Takumi Uezono, Kenichi Okada, Kazuya Masu: Via Distribution Model for Yield Estimation. 479-484
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  Lawrence S. Melvin III, Daniel N. Zhang, Kirk J. Strozewski, Skye Wolfer: The Use of the Manufacturing Sensitivity Model Forms to Comprehend Layout Manufacturing Robustness For Use During Device Design. 485-490
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  Robert C. Aitken: DFM Metrics for Standard Cells. 491-496
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  Arnaud Epinat, N. Vijayaraghavan, Matthieu Sautier, Olivier Callen, Sebastien Fabre, Ryan Ross, Paul Simon, Robin Wilson: Yield Enhancement Methodology for CMOS Standard Cells. 497-502
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  Hsin-Chyh Hsu, Ming-Dou Ker: Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask. 503-506

ISQED Panel Discussion 2

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  Ron Wilson, David Overhauser: Who is really responsible for quality throughout the design process?. 507

ISQED Plenary Session 2

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  Raul Camposano: Adding Manufacturability to the Quality of Results. 511
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  Changhyun Kim: Future Memory Technology Trends and Challenges. 513
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  H.-S. Philip Wong: Device and Technology Challenges for Nanoscale CMOS. 515-518

Session 4A: Analog Test and Self-Checking Design

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  Adam Matthews: A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard. 519-524
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  Qingqi Dou, Jacob A. Abraham: Jitter Decomposition by Time Lag Correlation. 525-530
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  Amit Laknaur, Haibo Wang: Design ofWindow Comparators for Integrator-Based Capacitor Array Testing Circuits. 531-536
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  Daniela De Venuto, Leonardo Reyneri: Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs. 537-542
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  José Luis Catalano, Gabriela Peretti, Eduardo Romero, Carlos A. Marqués: Exploring the Ability of Oscillation Based Test for Testing Continuous -Time Ladder Filters. 543-550

Session 4B: Power Aware Designs and Memory Management

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  Ozcan Ozturk, Mahmut T. Kandemir: Data Replication in Banked DRAMs for Reducing Energy Consumption. 551-556
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  Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson: Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. 557-563
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  Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos: Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. 564-569
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  Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Ozcan Ozturk: Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs. 570-575
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  Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu: Shared Scratch-Pad Memory Space Management. 576-584

Session 4C: Technologies for Robust Design

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  Wei Zhao, Yu Cao: New Generation of Predictive Technology Model for Sub-45nm Design Exploration. 585-590
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  M. Thomas, J. Pathak, J. Payne, F. Leisenberger, E. Wachmann, G. Schatzberger, A. Wiesner, Martin Schrems: A Non-Volatile Embedded Memory for High Temperature Automotive and High-Retention Applications. 591-596
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  Tai-Xiang Lai, Ming-Dou Ker: Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology. 597-602
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  Chung-Kuan Tsai, Malgorzata Marek-Sadowska: Analysis of Process Variation's Effect on SRAM's Read Stability. 603-610
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  Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. 611-616
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  Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar: Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. 617-624

Session 5A: IC-Package Design Challenges

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  Greg M. Link, Narayanan Vijaykrishnan: Thermal Trends in Emerging Technologies. 625-632
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  Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester: Power Gating with Multiple Sleep Modes. 633-637
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  Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan: SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching. 638-643
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  Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif: Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. 644-649
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  Mark M. Budnik, Kaushik Roy: Minimizing Ohmic Loss in Future Processor IR Events. 650-658

Session 5B: IP, Interoperability: Design Optimization

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  Anand P. Kulkarni, Thomas J. Grebinski: mTest: An Industry-Wide Database of VLSI Layouts for Quality Control. 659-664
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  Sanghamitra Roy, Charlie Chung-Ping Chen: ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. 665-670
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  Guangyu Sun, Zhiqiang Gao, Yi Xu: A Watermarking System for IP Protection by Buffer Insertion Technique. 671-675
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  Anand P. Kulkarni, Thomas J. Grebinski: Partial Selective Encryption: An Improved System for Protecting VLSI Design Data in the OASIS format. 676-681
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  Dimitri Kagaris, Themistoklis Haniotakis: Transistor-Level Optimization of Supergates. 682-690

Session 5C: DSM Interconnect Challenges

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  Andrew B. Kahng, Kambiz Samadi, Puneet Sharma: Study of Floating Fill Impact on Interconnect Capacitance. 691-696
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  Karen Chow: The Challenges and Impact of Parasitic Extraction at 65 nm. 697-702
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  Laureline David, Stephane Martin, Corinne Cregut, Eric Balossier, Frederic Nyer, Fabrice Huret: Pre-Layout Inductive Corners for Advanced Digital Design Interconnect: Modeling and Silicon Validation. 703-708
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  Changhao Yan, Wenjian Yu, Zeyi Wang: A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects. 709-716

Session 6A: Leakage Analysis and Optimization

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  Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula: LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. 717-722
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  Yu Wang, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang: Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization. 723-728
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  Behnam Amelifard, Massoud Pedram, Farzan Fallah: Low-leakage SRAM Design with Dual V_t Transistors. 729-734
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  Akhilesh Kumar, Mohab Anis: Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance. 735-740
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  Chanseok Hwang, Chang Woo Kang, Massoud Pedram: Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs. 741-746
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  Andrew B. Kahng, Swamy Muddu, Puneet Sharma: Impact of Gate-Length Biasing on Threshold-Voltage Selection. 747-754

Session 6B: System Level Designs and Reliability Models

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  Bin Zhang, Wei-Shen Wang, Michael Orshansky: FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. 755-760
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  Lee Barford: Diagnosis and Design for Diagnosability for Internet Routers. 761-768
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  Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao: Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. 769-774
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  Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada: Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. 775-780
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  Riad Ben Mouhoub, Omar Hammami: System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC. 781-788

Session 6C: Modeling for DFM

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  Artur Balasinski: Question: DRC or DfM ? Answer: FMEA and ROI. 789-794
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  Usha Narasimha, Binu Abraham, N. S. Nagaraj: Statistical Analysis of Capacitance Coupling Effects on Delay and Noise. 795-800
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  S. Tirumala, Y. Mahotin, Xiao Lin, Victor Moroz, Lee Smith, S. Krishnamurthy, L. Bomholt, Dipu Pramanik: Bringing Manufacturing into Design via Process-Dependent SPICE Models. 801-806
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  Victor Moroz, Lee Smith, Xi-Wei Lin, Dipu Pramanik, Greg Rollins: Stress-Aware Design Methodology. 807-812
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  Peter Wright, Minghui Fan: A DFM Methodology to Evaluate the Impact of Lithography Conditions on the Speed of Critical Paths in a VLSI Circuit. 813-817

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