ISPD 2009: San Diego, California, USA

• Carl J. Anderson:
  One look into the future of CMOS chip design. 1-2
  

Global layout planning

• Kai Wang, Aveek Sarkar, Norman Chang, Shen Lin:
  Early analysis for power distribution networks. 3-4
  
• Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang:
  Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs. 5-12
  
• Zaichen Qian, Evangeline F. Y. Young:
  Multi-voltage floorplan design with optimal voltage assignment. 13-18
  
• Jifeng Chen, Jin Sun, Janet Meiling Wang:
  Robust interconnect communication capacity algorithm by geometric programming. 19-26
  

Physical synthesis and circuit optimization

• Yifang Liu, Jiang Hu:
  A new algorithm for simultaneous gate sizing and threshold voltage assignment. 27-34
  
• Ashutosh Chakraborty, David Z. Pan:
  On stress aware active area sizing, gate sizing, and repeater insertion. 35-42
  
• Christoph Bartoschek, Stephan Held, Dieter Rautenbach, Jens Vygen:
  Fast buffering for optimizing worst slack and resource consumption in repeater trees. 43-50
  
• Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer:
  On improving optimization effectiveness in interconnect-driven physical synthesis. 51-58
  

Nanotechnology: CMOS and beyond

• Ruchir Puri:
  Will 22nm be our catch 22!: design and cad challenges. 59-60
  
• Stephen P. Kornachuk, Michael C. Smayling:
  New strategies for gridded physical design for 32nm technologies and beyond. 61-62
  
• Wojciech Maly:
  Vertical slit transistor based integrated circuits (VeSTICs) paradigm. 63-64
  
• Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli:
  Graphene based transistors: physics, status and future perspectives. 65-66
  

Analog design: tools and methodologies

• Anirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson:
  Accelerated design of analog, mixed-signal circuits in Titan. 67-72
  
• Eric Soenen:
  Physical design methodology for analog circuitsin a system-on-a-chip environment. 73-74
  
• Göran Jerke, Jens Lienig:
  Constraint-driven design: the next step towards analog design automation. 75-82
  

Layout optimization for FPGAs and regular fabrics

• Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
  Transistor-level layout of high-density regular circuits. 83-90
  
• Val Pevzner, Andrew A. Kennings, Andy Fox:
  Physical optimization for FPGAs using post-placement topology rewriting. 91-98
  
• Quang Dinh, Deming Chen, Martin D. F. Wong:
  A routing approach to reduce glitches in low power FPGAs. 99-106
  

Manufacturability and yield enhancement

• Kun Yuan, Jae-Seok Yang, David Z. Pan:
  Double patterning layout decomposition for simultaneous conflict and stitch minimization. 107-114
  
• Yang-Shan Tong, Chia-Wei Lin, Sao Jie Chen:
  An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization. 115-122
  
• Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang:
  Redundant via insertion with wire bending. 123-130
  
• Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng:
  Wire shaping is practical. 131-138
  

Clocking and the ISPD'09 clock synthesis contest

• Pei-Hsin Ho:
  Industrial clock design. 139-140
  
• Rupesh S. Shelar:
  An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. 141-148
  
• Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert:
  Ispd2009 clock network synthesis contest. 149-150
  

Advances in routing

• Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li:
  Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization. 151-158
  
• Tsung-Hsien Lee, Ting-Chi Wang:
  Robust layer assignment for via optimization in multi-layer global routing. 159-166
  
• Shiyan Hu, Zhuo Li, Charles J. Alpert:
  A faster approximation scheme for timing driven minimum cost layer assignment. 167-174
  
• Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
  Diffusion-driven congestion reduction for substrate topological routing. 175-180
  

Post-si prediction and debug

• Robert C. Aitken:
  The challenges of correlating silicon and models in high variability CMOS processes. 181-182
  
• Qunzeng Liu, Sachin S. Sapatnekar:
  Synthesizing a representative critical path for post-silicon delay prediction. 183-190
  
• Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang:
  A metal-only-ECO solver for input-slew and output-loading violations. 191-198
  

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