ISPD 2003: Monterey, CA, USA

@proceedings{DBLP:conf/ispd/2003,
  editor    = {Massoud Pedram and
               Charles J. Alpert},
  title     = {Proceedings of the 2003 International Symposium on Physical Design,
               ISPD 2003, Monterey, CA, USA, April 6-9, 2003},
  booktitle = {ISPD},
  publisher = {ACM},
  year      = {2003},
  isbn      = {1-58113-650-1},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Welcome and Keynote

• Raul Camposano:
  Keynote Speaker. 3
  

Placement and Physical Synthesis Deep Dive (invited)

• Paul Villarrubia:
  Important placement considerations for modern VLSI chips. 6
  
• Ravi Varadarajan:
  Convergence of placement technology in physical synthesis: is placement really a point tool? 7
  

Issues in Timing

• Ting-Yuan Wang, Yu-Min Lee, Charlie Chung-Ping Chen:
  3D thermal-ADI: an efficient chip-level transient thermal simulator. 10-17
  
• Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera:
  Capturing crosstalk-induced waveform for accurate static timing analysis. 18-23
  
• Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
  Closed form expressions for extending step delay and slew metrics to ramp inputs. 24-31
  
• Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee:
  Explicit gate delay model for timing evaluation. 32-38
  
• Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda:
  Signal integrity management in an SoC physical design flow. 39-46
  

From the Trenches (invited)

• Leon Stok, John M. Cohn:
  There is life left in ASICs. 48-50
  
• Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick:
  The scaling challenge: can correct-by-construction design help? 51-58
  

Partitioning & Placement

• Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin:
  Timing driven force directed placement with physical net constraints. 60-66
  
• Bo Hu, Malgorzata Marek-Sadowska:
  Fine granularity clustering for large scale placement problems. 67-74
  
• Guoqiang Chen, Sachin S. Sapatnekar:
  Partition-driven standard cell thermal placement. 75-80
  
• Andrew B. Kahng, Xu Xu:
  Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning. 81-86
  

Benchmarking

• Jason Cong, Michail Romesis, Min Xie:
  Optimality, scalability and stability study of partitioning and placement algorithms. 88-94
  
• Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden:
  Benchmarking for large-scale placement and beyond. 95-103
  

Power Grid Design (invited)

• Raymond X. Nijssen, Ed P. Huijbregts:
  A complete design for power methodology and flow for large ASICs. 106-108
  

Lithography and Routing: What's Next? (invited)

• Lars Liebmann:
  Layout impact of resolution enhancement techniques: impediment or opportunity? 110-117
  
• Hardy Kwok-Shing Leung:
  Advanced routing in changing technology landscape. 118-121
  
• Andrew B. Kahng:
  Research directions for coevolution of rules and routers. 122-125
  

Floorplanning

• Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang:
  Constrained "Modern" Floorplanning. 128-135
  
• Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
  An integrated floorplanning with an efficient buffer planning algorithm. 136-142
  
• Matthew Moe, Herman Schmit:
  Floorplanning of pipelined array modules using sequence pairs. 143-150
  

Routing and Clocking

• Hai Zhou:
  Efficient Steiner tree construction based on spanning graphs. 152-157
  
• Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay:
  Porosity aware buffered steiner tree construction. 158-165
  
• Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen:
  Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time. 166-173
  
• Bing Lu, Jiang Hu, Gary Ellis, Haihua Su:
  Process variation aware clock tree routing. 174-181
  

Regular Circuit Fabrics (invited)

• Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi:
  An architectural exploration of via patterned gate arrays. 184-189
  
• Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang:
  Architecture and synthesis for multi-cycle communication. 190-196
  
• Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska:
  Synthesis and placement flow for gain-based programmable regular fabrics. 197-203
  
• Fan Mo, Robert K. Brayton:
  Fishbone: a block-level placement and routing scheme. 204-209
  

Last update Wed Feb 15 05:11:36 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page