ISPD 1999: Monterey, CA, USA

• Desmond Kirkpatrick:
  The deep sub-micron signal integrity challenge. 4-7
  
• Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, Takashi Omachi:
  A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design. 9-15
  
• Sachio Hayashi, Masaaki Yamada:
  EMI-noise analysis under ASIC design environment. 16-21
  
• Paul B. Morton, Wayne Wei-Ming Dai:
  An efficient sequential quadratic programming formulation of optimal wire spacing for cross-talk noise avoidance routing. 22-28
  
• Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai:
  Post-routing timing optimization with routing characterization. 30-35
  
• X. Zeng, D. Zhou, Wei Li:
  Buffer insertion for clock delay and skew minimization. 36-41
  
• Yanhong Yuan, Prithviraj Banerjee:
  Incremental capacitance extraction and its application to iterative timing-driven detailed routing. 42-47
  
• Kevin T. Tang, Eby G. Friedman:
  Interconnect coupling noise in CMOS VLSI circuits. 48-53
  
• Jeff Parkhurst, Naveed A. Sherwani, Sury Maturi, Dana Ahrams, Eli Chiprout:
  SRC physical design top ten problem. 55-58
  
• Dirk Stroobandt, Peter Verplaetse, Jan Van Campenhout:
  Towards synthetic benchmark circuits for evaluating timing-driven CAD tools. 60-66
  
• Joachim Pistorius, Edmée Legai, Michel Minoux:
  Generation of very large circuits to benchmark the partitioning of FPGA. 67-73
  
• Michael A. Riepe, Karem A. Sakallah:
  Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis. 74-81
  
• Patrick H. Madden:
  Partitioning by iterative deletion. 83-89
  
• Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
  Optimal partitioners and end-case placers for standard-cell layout. 90-96
  
• Fung Yu Young, D. F. Wong:
  Slicing floorplans with range constraint. 97-102
  
• Kunihiro Fujiyoshi, Hiroshi Murata:
  Arbitrary convex and concave rectilinear block packing using sequence-pair. 103-110
  
• Andrew B. Kahng, Y. C. Pati:
  Subwavelength optical lithography: challenges and impact on physical design. 112-119
  
• Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Huijuan Wang, Alexander Zelikovsky:
  Optimal phase conflict removal for layout of dark field alternating phase shifting masks. 121-126
  
• Wei Chen, Cheng-Ta Hsieh, Massoud Pedram:
  Gate sizing with controlled displacement. 127-132
  
• Jiang Hu, Sachin S. Sapatnekar:
  Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model. 133-138
  
• Joseph L. Ganley:
  Efficient solution of systems of orientation constraints. 140-144
  
• Maogang Wang, Majid Sarrafzadeh:
  On the behavior of congestion minimization during placement. 145-150
  
• Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
  Partitioning with terminals: a "new" problem and new benchmarks. 151-157
  
• Durgam Vahia, Maciej J. Ciesielski:
  Transistor level placement for full custom datapath cell design. 158-163
  
• Amit Singh, Malgorzata Marek-Sadowska:
  Circuit clustering using graph coloring. 164-169
  
• Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang:
  Interconnect thermal modeling for determining design limits on current density. 172-178
  
• Ching-Han Tsai, Sung-Mo Kang:
  Standard cell placement for even on-chip thermal distribution. 179-184
  
• Kusnadi, Jo Dale Carothers:
  A method of measuring nets routability for MCM's general area routing problems. 186-192
  
• Dennis Sylvester, Kurt Keutzer:
  Getting to the bottom of deep submicron II: a global wiring paradigm. 193-200
  
• Phiroze N. Parakh, Richard B. Brown:
  Crosstalk constrained global route embedding. 201-206
  
• Sung-Woo Hur, Ashok Jagannathan, John Lillis:
  Timing driven maze routing. 208-213
  
• Jason Cong, Jie Fang, Kei-Yong Khoo:
  VIA design rule consideration in multi-layer maze routing algorithms. 214-220
  

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