ISPD 1998: Monterey, CA, USA

• Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky:
  On wirelength estimations for row-based placement. 4-11
  
• Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin:
  Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. 12-17
  
• Kia Bazargan, Samjung Kim, Majid Sarrafzadeh:
  Nostradamus: a floorplanner of uncertain design. 18-23
  
• Lawrence T. Pileggi:
  Timing metrics for physical design of deep submicron technologies. 28-33
  
• Wojciech Maly:
  Moore's law and physical design of ICs. 36
  
• Chris C. N. Chu, D. F. Wong:
  Greedy wire-sizing is linear time. 39-44
  
• Jason Cong, Lei He:
  An efficient technique for device and interconnect optimization in deep submicron designs. 45-51
  
• Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley:
  Device-level early floorplanning algorithms for RF circuits. 57-64
  
• Akira Nagao, Takashi Kambe, Isao Shirakawa:
  A layout approach to monolithic microwave IC. 65-72
  
• S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, Amrich Chokhavtia:
  CHDStd - application support for reusable hierarchical interconnect timing views. 75-79
  
• Charles J. Alpert:
  The ISPD98 circuit benchmark suite. 80-85
  
• S. DasGupta:
  Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel). 86
  
• Evanthia Papadopoulou, D. T. Lee:
  Critical area computation - a new approach. 89-94
  
• Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky:
  Filling and slotting: analysis and algorithms. 95-102
  
• Ralph H. J. M. Otten:
  Global wires: harmful?. 104-109
  
• Shantanu Dutt, Halim Theny:
  Partitioning using second-order information and stochastic-gain functions. 112-117
  
• Zhaoyun Xing, Prithviraj Banerjee:
  A parallel algorithm for zero skew clock tree routing. 118-123
  
• Temo Chen, Michael K. H. Fan:
  On convex formulation of the floorplan area minimization problem. 124-128
  
• Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas:
  A pattern matching algorithm for verification and analysis of very large IC layouts. 129-134
  
• Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng:
  LIBRA - a library-independent framework for post-layout performance optimization. 135-140
  
• Sudhakar Bobba, Ibrahim N. Hajj:
  Estimation of maximum current envelope for power bus analysis and design. 141-146
  
• Andrew B. Kahng, Sudhakar Muddu:
  New efficient algorithms for computing effective capacitance. 147-151
  
• Payam Heydari, Massoud Pedram:
  Calculation of ramp response of lossy transmission lines using two-port network functions. 152-157
  
• Guang-Ming Wu, Yao-Wen Chang:
  Switch-matrix architecture and routing for FPDs. 158-163
  
• Hiroshi Murata, Ernest S. Kuh:
  Sequence-pair based placement method for hard/soft/pre-placed modules. 167-172
  
• Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng:
  Rectilinear block placement using sequence-pair. 173-178
  
• Maggie Zhiwei Kang, Wayne Wei-Ming Dai:
  Topology constrained rectilinear block packing for layout reuse. 179-186
  
• Andrew B. Kahng:
  Futures for partitioning in physical design (tutorial). 190-193
  
• Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen:
  Chip-level area routing. 197-204
  
• Huibo Hou, Sachin S. Sapatnekar:
  Routing tree topology construction to meet interconnect timing constraints. 205-210
  
• Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl:
  Analysis, reduction and avoidance of crosstalk on VLSI chips. 211-218
  

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