ISPASS 2011: Austin, TX, USA
IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2011, 10-12 April, 2011, Austin, TX, USA. IEEE Computer Society 2011 ISBN 978-1-61284-367-4
Keynote I
- Ravishankar Iyer: Keynote I: The era of heterogeneity: Are we prepared? 1
Session 1: Best Paper Nominees
- Carole-Jean Wu, Margaret Martonosi: Characterization and dynamic mitigation of intra-application cache interference. 2-11
- Junghee Lee, Youngjae Kim, Galen M. Shipman, Sarp Oral, Feiyi Wang, Jongman Kim: A semi-preemptive garbage collector for solid state drives. 12-21
- Jeffrey R. Diamond, Martin Burtscher, John D. McCalpin, Byoung-Do Kim, Stephen W. Keckler, James C. Browne: Evaluation and optimization of multicore performance bottlenecks in supercomputing applications. 32-43
Session 2: Memory Hierarchies
- Christina M. Patrick, Nicholas Voshell, Mahmut T. Kandemir: Minimizing interference through application mapping in multi-level buffer caches. 44-55
- Santiago Bock, Bruce R. Childers, Rami G. Melhem, Daniel Mossé, Youtao Zhang: Analyzing the impact of useless write-backs on the endurance and energy consumption of PCM main memory. 56-65
- Hyojin Choi, Jongbok Lee, Wonyong Sung: Memory access pattern-aware DRAM performance model for multi-core systems. 66-75
- Tanima Dey, Wei Wang, Jack W. Davidson, Mary Lou Soffa: Characterizing multi-threaded applications based on shared-resource contention. 76-86
Session 3: Tracing
- Alejandro Rico, Alejandro Duran, Felipe Cabarcas, Yoav Etsion, Alex Ramírez, Mateo Valero: Trace-driven simulation of multithreaded applications. 87-96
Poster Session
- Dan Upton, Kim M. Hazelwood: Finding cool code: An analysis of source-level causes of temperature effects. 117-118
- Jiayuan Meng, Kevin Skadron: A reconfigurable simulator for large-scale heterogeneous multicore architectures. 119-120
- David Meisner, Junjie Wu, Thomas F. Wenisch: Towards a scalable data center-level evaluation methodology. 121-122
- Christina Delimitrou, Sriram Sankar, Kushagra Vaid, Christos Kozyrakis: Storage I/O generation and replay for datacenter applications. 123-124
- Alexandra Jimborean, Matthieu Herrmann, Vincent Loechner, Philippe Clauss: VMAD: A virtual machine for advanced dynamic analysis of programs. 125-126
- Mohamed F. Ahmed, Omar Haridy: A comparative benchmarking of the FFT on Fermi and Evergreen GPUs. 127-128
- Andreas Genser, Christian Bachmann, Christian Steger, Reinhold Weiss, Josef Haid: Supply voltage emulation platform for DVFS voltage drop compensation explorations. 129-130
- Michelle McDaniel, Kim M. Hazelwood: Performance characterization of mobile-class nodes: Why fewer bits is better. 131-132
Keynote II
- Pradip Bose: Keynote II: Integrated modeling challenges in extreme-scale computing. 133
Session 4: Emerging Workloads
- Chris Gregg, Kim M. Hazelwood: Where is the data? Why you cannot debate CPU vs. GPU performance without the answer. 134-144
- Guangyu Shi, Min Li, Mikko H. Lipasti: Accelerating search and recognition workloads with SSE 4.2 string and text processing instructions. 145-153
- Zhenman Fang, Donglei Yang, Weihua Zhang, Haibo Chen, Binyu Zang: A comprehensive analysis and parallelization of an image retrieval algorithm. 154-164
- Mathias Payer, Thomas R. Gross: Performance evaluation of adaptivity in software transactional memory. 165-174
Session 5: Simulation and Modeling
- Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan, Srinivas Devadas: Scalable, accurate multicore simulation in the 1000-core era. 175-185
- David A. Penry: A single-specification principle for functional-to-timing simulator interface design. 186-196
- Kermin Elliott Fleming, Man Cheuk Ng, Samuel Gross, Arvind: WiLIS: Architectural modeling of wireless systems. 197-206
- Michael Kistler, Daniel A. Brokenshire: Detecting race conditions in asynchronous DMA operations with full system simulation. 207-215
- Stijn Eyerman, Kenneth Hoste, Lieven Eeckhout: Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. 216-226
Session 6: Power and Reliability
- Chung-Hsing Hsu, Stephen W. Poole: Power signature analysis of the SPECpower_ssj2008 benchmark. 227-236
- Jungseob Lee, Paritosh Pratap Ajgaonkar, Nam Sung Kim: Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation. 237-246
- Lide Duan, Ying Zhang, Bin Li, Lu Peng: Universal rules guided design parameter selection for soft error resilient processors. 247-256
- Seung-Hwan Lim, Bikash Sharma, Byung-Chul Tak, Chita R. Das: A dynamic energy management scheme for multi-tier data centers. 257-266
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last updated on 2013-06-18T214307 by the dblp team