Keynote

• 
  David A. Patterson: RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform. 1

Accelerating Simulation

• 
  Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe: Simulation sampling with live-points. 2-12
• 
  Rose F. Liu, Krste Asanovic: Accelerating architectural exploration using canonical instruction segments. 13-24
• 
  Kenneth C. Barr, Krste Asanovic: Branch trace compression for snapshot-based simulation. 25-36

Microarchitecture Performance Evaluation

• 
  Ramadass Nagarajan, Xia Chen, Robert G. McDonald, Doug Burger, Stephen W. Keckler: Critical path analysis of the TRIPS architecture. 37-47
• 
  Stijn Eyerman, James E. Smith, Lieven Eeckhout: Characterizing the branch misprediction penalty. 48-58
• 
  Gabriel H. Loh: Revisiting the performance impact of branch predictor latencies. 59-69

Statistical Models

• 
  Ajay Joshi, Joshua J. Yi, Robert H. Bell Jr., Lieven Eeckhout, Lizy Kurian John, David J. Lilja: Evaluating the efficacy of statistical simulation for design space exploration. 70-79
• 
  Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar: Comparing simulation techniques for microarchitecture-aware floorplanning. 80-88
• 
  Erik Berg, Håkan Zeffer, Erik Hagersten: A statistical multiprocessor cache model. 89-99

Power

• 
  Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian: Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. 100-111
• 
  Huaping Wang, Yao Guo, Israel Koren, C. Mani Krishna: Compiler-based adaptive fetch throttling for energy-efficiency. 112-119
• 
  Banit Agrawal, Timothy Sherwood: Modeling TCAM power for next generation network devices. 120-129

Keynote

• 
  Mary K. Vernon: Quantitative system design. 130

Simulation Methodologies and Validation

• 
  Greg Hamerly, Erez Perelman, Brad Calder: Comparing multinomial and k-means clustering for SimPoint. 131-142
• 
  Michael Van Biesbrouck, Lieven Eeckhout, Brad Calder: Considering all starting points for simultaneous multithreading simulation. 143-153
• 
  Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John, Jeff Stuecheli, John Griswell, Paul Tu, Louis Capps, Anton Blanchard, Ravel Thai: Automatic testcase synthesis and performance model validation for high performance PowerPC processors. 154-165

Caches and Prefetching

• 
  Hassan Al-Sukhni, James Holt, Daniel A. Connors: Improved stride prefetching using extrinsic stream characteristics. 166-176
• 
  Natalie D. Enright Jerger, Eric L. Hill, Mikko H. Lipasti: Friendly fire: understanding the effects of multiprocessor prefetches. 177-188
• 
  Xiaoning Ding, Dimitrios S. Nikolopoulos, Song Jiang, Xiaodong Zhang: MESA: reducing cache conflicts by integrating static and run-time methods. 189-198

Workload Analysis

• 
  Rui Zhang, Zoran Budimlic, Ken Kennedy: Performance modeling and prediction for scientific Java applications. 199-210
• 
  Adriano M. Pereira, Leonardo Silva, Wagner Meira Jr., Walter Santos: Assessing the impact of reactive workloads on the performance of Web applications. 211-220
• 
  Dror G. Feitelson, Dan Tsafrir: Workload sanitation for performance evaluation. 221-230

Simulators and Tools

• 
  Victor Moya Del Barrio, Carlos González, Jordi Roca, Agustin Fernández, Roger Espasa: ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. 231-241
• 
  Simon Albert, Sven Kalms, Christian Weiss, Achim Schramm: Acquisition and evaluation of long DDR2-SDRAM access sequences. 242-250
• 
  Paul Berube, José Nelson Amaral: Aestimo: a feedback-directed optimization evaluation tool. 251-260

last updated on Sun May 26 04:14:19 2013 by the dblp team
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