Keynote Address

• 
  C. M. Allen: Multi-Valued Logic: Wave of the Future or an Historical Anachronism. 1

Circuits

• 
  Jonathan Wayne Mills, M. Gordon Beavers, Charles A. Daffinger: Lukasiewicz Logic Arrays. 4-10
• 
  Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto: On Design of Multiple-Valued Static Random-Access-Memory. 11-17
• 
  Takahiro Hanyu, Tatsuo Higuchi: Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. 18-23
• 
  J. M. Johnson: Ternary Logic Elements for Self-timed Integrated Systems. 24
• 
  Orlando E. Katter Jr., Hassan M. Razavi: A New CMOS Gate - The Balanced Gate - For Detecting Physical Failures. 25-31

Algebra I

• 
  Lucien Haddad, Ivo G. Rosenberg: A Note on Finite Clones Containing All Permutations. 34-41
• 
  George Epstein, Helena Rasiowa: Theory and Uses of Post Algebras of Order omega+omegaw\ast.I. 42-47
• 
  Corina Reischer, Dan A. Simovici: Bio-Algebras. 48-53
• 
  Louis H. Kaufman: Robbins Algebra. 54-60

Spectral Techniques

• 
  Claudio Moraga, Jörg Poswig: Properties of the Zhang-Hartley Spectrum of Patterns. 62-68
• 
  T. Raju Damarla: Fault Detection in Multiple Valued Logic Circuits. 69-74
• 
  Bogdan J. Falkowski, Marek A. Perkowski: Walsh Type Transforms for Completely and Incompletely Specified Multiple-Valued Input Binary Functions. 75-82

Algebra II

• 
  Aldo V. Figallo, Luiz Monteiro, Alicia Ziliani: Free Three-valued Lukasiewicz, Post and Moisil Algebras over a Poset. 433-435
• 
  Josep Maria Font, Miquel Rius: A Four-Valued Modal Logic Arising from Monteiro's Last Algebras. 85-92
• 
  Noboru Takagi, Masao Mukaidono: Kleene-Stone Logic Functions. 93-100

Special Applications I

• 
  Deepak Dube, Anneliese von Mayrhauser: Alleviating Memory Bottlenecks Using Multi-Level Memory. 102-109
• 
  Oscar N. Garcia, Massoud Moussavi: A Six-Valued Logic for Representing Incomplete Knowledge. 110-114
• 
  A. Sengupta, C. Rhee: On the Diagnosability of Systems with Three Valued Test Results: Diagnosis by Comparison Strategy. 115-120
• 
  Jia-Yuan Han, Supreet Singh: Comparison Look-Ahead and Design of Fast Fuzzy Operation Units. 121-125

Logic Design I

• 
  Tsutomu Sasao: EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions. 128-135
• 
  Gerhard W. Dueck, D. Michael Miller: RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. 136-143
• 
  John M. Yurchak, Jon T. Butler: HAMLET - An Expression Compiler/Optimizer for the Implementation of Heuristics to Minimize Multiple-Valued Programmable Logic Arrays. 144-152
• 
  Chyan Yang, Yao-Ming Wang: A Neighborhood Decoupling Algorithm for Truncated Sum Minimization. 153-160

Invited Address

• 
  Michitaka Kameyama: Toward the Age of Beyond-Binary Electronics and Systems. 162-166

Circuits II

• 
  K. Wayne Current: A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. 168-173
• 
  Debashis Bhattacharya: Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer. 174-180
• 
  Peter Baltus, Pieter van der Meulen, Ross Morley: An Efficient Multi-Level Multi-Wire Differential Interface. 181-188
• 
  Lutz J. Micheel, Michael J. Paulus: Differential Multiple-Valued Logic Using Resonant Tunneling Diodes. 189-195
• 
  Mou Hu, Kenneth C. Smith: Application of Multiple-Valued Switch-Level Algebra to the Design and Analysis of Pass-Transistor Switch Networks. 196-201

Logic

• 
  Zbigniew Stachniak: Note on Resolution Approximation of Many-Valued Logics. 204-209
• 
  I. R. Goodman: Conditional Event Algebras and Logic, Part I: Motivation and History of the Problem. 210
• 
  Michael F. Schmidt: On Some Neglected Paradoxes of Modem Logic. 211-219
• 
  Nuno J. Mamede, João P. Martins: Bringing Resources into Logic. 220-227
• 
  Kazimierz Trzesicki: Many-Valued Tense Logic and the Problem of Determinism. 228-236

Invited Address

• 
  Melvin Fitting: Bilattices in Logic Prograrnming. 238-246

Logic and Algebra

• 
  János Demetrovics, Masahiro Miyakawa, Ivo G. Rosenberg, Dan A. Simovici, Ivan Stojmenovic: Intersections of Isotone Clones on a Finite Set. 248-253
• 
  Masahiro Miyakawa, Ivan Stojmenovic, Dietlinde Lau, Taketoshi Mishima: On the Structure of Maximal Closed Sets of P_K2. 254-261
• 
  Hantao Zhang: Approximate Reasoning in Strength Logic. 262-269
• 
  O. O. Silva, C. R. Souza: Induction of Fuzzy Production Rules. 270-278
• 
  Lichun Cheng, Mou Hu: A General Fuzzy Logical Operator Set. 279-283

Logic Design II

• 
  Jon T. Butler, Hans G. Kerkhoff, Siep Onneweer: A Comparative Analysis of Multiplexer Techniques for the Minimization of Function Cost Using the Costtable Approach. 286-291
• 
  Jon C. Muzio: Concerning the Maximum Size of the Terms in the Realization of Symmetric Functions. 292-299
• 
  Safwat G. Zaky, Zvonko G. Vranesic, Mostafa H. Abd-El-Barr: Step-Wise Synthesis of CCD MVL Functions. 300-307
• 
  Srinivas Devadas: Minimization of Functions with Multiple-Valued Outputs: Theory and Applications. 308-315
• 
  Mostafa H. Abd-El-Barr, H. Choy: On the Synthesis of MVMT Functions for PLA Implementation Using CCDs. 316-323

Invited Address

• 
  Ryszard S. Michalski: Theory of Plausible Reasoning - Foundations and Methodology. 325

Logic and Artificial Intelligence

• 
  Walter Alexandre Carnielli: Many-Valued Logics and Plausible Reasoning. 328-335
• 
  Masamitu Otake, Taketoshi Mishima, Yoichi Manome: Strength of the Rule of Inference. 336-338
• 
  V. S. Subrahmanian: Paraconsistent Disjunctive Deductive Databases. 339-346

Circuits III

• 
  Daniel Etiemble, C. Chanussot, Vincent Néri: 4-Valued BiCMOS Circuits for the Transmission System of a Massively Parallel Architecture. 348-354
• 
  Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi: Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. 355-362
• 
  Hsu Liang Ho, Kenneth C. Smith: Integrator-Chain Multiplier. 363-369

Artificial Intelligence and Expert Systems

• 
  Zbigniew W. Ras: Fault-Recovery and Intelligent Distributed System. 372-377
• 
  W. Elliott Jr., M. Schneider: The Learning Aspects of the Fault Finder Expert System. 378-385
• 
  Rudolf Felix: Goal-Oriented Control of VLSI Design Processes Based on Fuzzy Sets. 386-393
• 
  Zhijian Li, Hong Jiang: A CMOS Current-Mode High Speed Fuzzy Logic Microprocessor for a Real-Time Expert System. 394-401

Special Applications II

• 
  Kevin Cattell, Micaela Serra: The Analysis of One Dimensional Multiple-Valued Linear Cellular Automata. 402-409
• 
  Yutaka Hata, Kyoichi Nakashima, Kazuharu Yamato: Some Relationships Between Multiple-Valued Kleenean Functions and Ternary Input Multiple-Valued Output Functions. 410-417
• 
  Tatsuki Watanabe, Masayuki Matsumoto, Mitsuaki Enokida, Takahiro Hasegawa: A Design of Multiple-Valued Logic Neuron. 418-425
• 
  Loke-Soo Hsu, Hoon heng Teh, Sing-Chai Chan, Kia-Fock Loe: Multi-Valued Neural Logic Networks. 426-432

last updated on Wed May 22 04:50:33 2013 by the dblp team
data released under the ODC-BY 1.0 license
see also our legal information page