ISLPED 2007: Portland, OR, USA

• Robert Chau:
  Nanotechnology for low-power and high-speed nanoelectronics applications. 1
  

Emerging device technologies for low power

• Asha Balijepalli, Saurabh Sinha, Yu Cao:
  Compact modeling of carbon nanotube transistor for early stage process-design exploration. 2-7
  
• Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang:
  A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. 8-13
  
• Yu Zhou, Shijo Thekkel, Swarup Bhunia:
  Low power FPGA design using hybrid CMOS-NEMS approach. 14-19
  
• Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang:
  Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. 20-25
  
• Michael T. Niemier, M. Alam, Xiaobo Sharon Hu, Gary H. Bernstein, Wolfgang Porod, M. Putney, J. DeAngelis:
  Clocking structures and power analysis for nanomagnet-based logic devices. 26-31
  

Power-efficient CMP design

• Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester:
  Energy efficient near-threshold chip multi-processing. 32-37
  
• Sebastian Herbert, Diana Marculescu:
  Analysis of dynamic voltage/frequency scaling in chip-multiprocessors. 38-43
  
• Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose:
  Evaluating design tradeoffs in on-chip power management for CMPs. 44-49
  
• Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson:
  Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. 50-55
  
• Sungjune Youn, Hyunhee Kim, Jihong Kim:
  A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches. 56-61
  

Low-power techniques for logic, clock distribution, and interconnect

• Sherif A. Tawfik, Volkan Kursun:
  Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. 62-67
  
• Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy:
  A robust edge encoding technique for energy-efficient multi-cycle interconnect. 68-73
  
• Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy:
  Low-power process-variation tolerant arithmetic units using input-based elastic clocking. 74-79
  
• Jie Gu, Hanyong Eom, Chris H. Kim:
  Sleep transistor sizing and control for resonant supply noise damping. 80-85
  
• Ja Chun Ku, Yehea I. Ismail:
  Thermal-aware methodology for repeater insertion in low-power VLSI circuits. 86-91
  

Power considerations at the physical level

• Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang:
  Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. 92-97
  
• Hanif Fatemi, Behnam Amelifard, Massoud Pedram:
  Power optimal MTCMOS repeater insertion for global buses. 98-103
  
• Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
  Timing-driven row-based power gating. 104-109
  
• Andrew B. Kahng, Swamy Muddu, Puneet Sharma:
  Detailed placement for leakage reduction using systematic through-pitch variation. 110-115
  
• Imad A. Ferzli, Farid N. Najm, Lars Kruse:
  Early power grid verification under circuit current uncertainties. 116-121
  
• Shekhar Borkar, William J. Dally:
  Future of on-chip interconnection architectures. 122
  

Software and system power optimization

• Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David Brooks:
  Towards a software approach to mitigate voltage emergencies. 123-128
  
• Mahmut T. Kandemir, Seung Woo Son, Mustafa Karaköy:
  Improving disk reuse for reducing power consumption. 129-134
  
• Youngjin Cho, Younghyun Kim, Naehyuck Chang:
  PVS: passive voltage scaling for wireless sensor networks. 135-140
  
• Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li:
  A programming environment with runtime energy characterization for energy-aware applications. 141-146
  

Leakage-aware architectural synthesis

• Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy:
  A process variation aware low power synthesis methodology for fixed-point FIR filters. 147-152
  
• Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel:
  Voltage- and ABB-island optimization in high level synthesis. 153-158
  
• Simone Medardoni, Davide Bertozzi, Enrico Macii:
  Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies. 159-164
  
• Quming Zhou, Lin Zhong, Kartik Mohanram:
  Power signal processing: a new perspective for power analysis and optimization. 165-170
  

Low-power memory design and NBTI detection

• Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy:
  A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. 171-176
  
• Keejong Kim, Hamid Mahmoodi, Kaushik Roy:
  A low-power SRAM using bit-line charge-recycling technique. 177-182
  
• Kimish Patel, Wonbok Lee, Massoud Pedram:
  Minimizing power dissipation during write operation to register files. 183-188
  
• John Keane, Tae-Hyoung Kim, Chris H. Kim:
  An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. 189-194
  
• Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh:
  Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. 195-200
  

DVS and thermal management

• Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti:
  Throughput of multi-core processors under thermal constraints. 201-206
  
• Gaurav Dhiman, Tajana Simunic Rosing:
  Dynamic voltage frequency scaling for multi-tasking systems using online learning. 207-212
  
• Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose:
  Thermal-aware task scheduling at the system software level. 213-218
  
• Heather Hanson, Stephen W. Keckler, Soraya Ghiasi, Karthick Rajamani, Freeman L. Rawson III, Juan Rubio:
  Thermal response to DVFS: analysis with an Intel Pentium M. 219-224
  
• Sushu Zhang, Karam S. Chatha, Goran Konjevod:
  Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. 225-230
  
• David A. Patterson:
  The parallel computing landscape: a Berkeley view. 231
  

Signal processing, wireless, and communication

• Sizhong Chen, Tong Zhang:
  Low power soft-output signal detector design for wireless MIMO communication systems. 232-237
  
• Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo Jeong, Suk Joong Lee, Hoi-Jun Yoo:
  A low power multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG for mobile devices. 238-243
  
• Ravi Jenkal, W. Rhett Davis:
  An architecture for energy efficient sphere decoding. 244-249
  
• Yang Liu, Tong Zhang:
  On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing. 250-255
  
• Ke Xu, Chiu-sing Choy:
  Low-power H.264/AVC baseline decoder for portable applications. 256-261
  

Architectural power optimization

• Vivienne Sze, Anantha P. Chandrakasan:
  A 0.4-V UWB baseband processor. 262-267
  
• Michael D. Powell, T. N. Vijaykumar:
  Resource area dilation to reduce power density in throughput servers. 268-273
  
• Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino:
  Locality-driven architectural cache sub-banking for leakage energy reduction. 274-279
  
• Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. dos Santos:
  A multi-model power estimation engine for accuracy optimization. 280-285
  

DC/DC converters

• Minkyu Song, Dongsheng Ma:
  A fast-transient over-sampled delta-sigma adaptive DC-DC converter for power-efficient noise-sensitive devices. 286-291
  
• Han Shiming, Wu Xiaobo, Liu Yang:
  High-efficiency synchronous dual-output switched-capacitor dc-dc converter with digital state machine control. 292-297
  
• Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
  A micro power management system and maximum output power control for solar energy harvesting applications. 298-303
  
• David E. Duarte, Greg Taylor, Keng L. Wong, Usman Mughal, George Geannopoulos:
  Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor. 304-309
  
• Min Chen, Gabriel A. Rincón-Mora:
  Single inductor, multiple input, multiple output (SIMIMO) power mixer-charger-supply system. 310-315
  

Energy and power delivery

• Lu Chao, Chi-Ying Tsui, Wing-Hung Ki:
  Vibration energy scavenging and management for ultra low power applications. 316-321
  
• Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang:
  Energy management of DVS-DPM enabled embedded systems powered by fuel cell-battery hybrid source. 322-327
  
• Behnam Amelifard, Massoud Pedram:
  Design of an efficient power delivery network in an soc to enable dynamic power management. 328-333
  
• Jen-Wei Hsieh, Tei-Wei Kuo, Po-Liang Wu, Yu-Chung Huang:
  Energy-efficient and performance-enhanced disks using flash-memory cache. 334-339
  
• Praveen Bhojwani, Jason D. Lee, Rabi N. Mahapatra:
  SAPP: scalable and adaptable peak power management in nocs. 340-345
  
• Luiz André Barroso:
  All watts considered. 346
  

Posters

• Martin Saint-Laurent, Baker Mohammad, Paul Bassett:
  A 65-nm pulsed latch with a single clocked transistor. 347-350
  
• Aveek Sarkar, Shen Lin, Kai Wang:
  A methodology for analysis and verification of power gated circuits with correlated results. 351-354
  
• Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
  V_t balancing and device sizing towards high yield of sub-threshold static logic gates. 355-358
  
• Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto:
  Power-efficient LDPC code decoder architecture. 359-362
  
• Mohamed Kawokgy, C. Andre T. Salama:
  A low-power CSCD asynchronous viterbi decoder for wireless applications. 363-366
  
• Mingming Zhang, Xiaotao Chang, Ge Zhang:
  Reducing cache energy consumption by tag encoding in embedded processors. 367-370
  
• Enric Morancho, José María Llabería, Àngel Olivé:
  On reducing energy-consumption by late-inserting instructions into the issue queue. 371-374
  
• Erika Gunadi, Mikko H. Lipasti:
  Power-aware operand delivery. 375-378
  
• Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni:
  On the latency, energy and area of checkpointed, superscalar register alias tables. 379-382
  
• Zhenhua Wang:
  Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design. 383-386
  
• Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy:
  Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. 387-390
  
• Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska:
  Electromigration and voltage drop aware power grid optimization for power gated ICs. 391-394
  
• Jung-Hi Min, Hojung Cha:
  Reducing display power in DVS-enabled handheld systems. 395-398
  
• Balasubramanian Sethuraman, Ranga Vemuri:
  Multicasting based topology generation and core mapping for a power efficient networks-on-chip. 399-402
  
• Konrad Malkowski, Padma Raghavan, Mahmut T. Kandemir, Mary Jane Irwin:
  Phase-aware adaptive hardware selection for power-efficient scientific computations. 403-406
  
• Julien Mercier, Christian Dufaza, Mathieu Lisart:
  Signoff power methodology for contactless smartcards. 407-410
  
• Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son:
  An ilp based approach to reducing energy consumption in nocbased CMPS. 411-414
  

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