Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy (Eds.):
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004.
Newport Beach, California, USA
Circuit challenges for scaled technologies
Microarchitecural techniques for power reduction
Cache and bus design
System design methodologies
, Jason Cong
: Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.
Technologies and devices for low-power
Power optimizations for cache memory
, Chien-Hao Lee
: HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction.
Leakage analysis and optimization
, Pai H. Chou
: Maximizing efficiency of solar-powered systems by load matching.
Power supply, voltage, and frequency management
Power-efficient bus design
High level power modeling and analysis
Low power converter circuits
Circuits for low power wireless
Power efficient design for arithmetic circuits
Energy efficient architectural techniques
Kim M. Hazelwood
, David Brooks
: Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization.
: Application adaptive energy efficient clustered architectures.
Wireless application drivers for low-power systems
Adaptive voltage scaling