ISLPED 2001: Huntington Beach, California, USA

@proceedings{DBLP:conf/islped/2001,
  editor    = {Enrico Macii and
               Vivek De and
               Mary Jane Irwin},
  title     = {Proceedings of the 2001 International Symposium on Low Power
               Electronics and Design, 2001, Huntington Beach, California, USA,
               2001},
  booktitle = {ISLPED},
  publisher = {ACM},
  year      = {2001},
  isbn      = {1-58113-371-5},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Jan M. Rabaey:
  Wireless beyond the third generation wireless beyond the third generation: facing the energy challenge. 1-3
  
• Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen:
  Micro-operation cache: a power aware frontend for the variable instruction length ISA. 4-9
  
• Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
  L1 data cache decomposition for energy efficiency. 10-15
  
• Amirali Baniasadi, Andreas Moshovos:
  Instruction flow-based front-end throttling for power-aware high-performance processors. 16-21
  
• Vasily G. Moshnyaga:
  Energy reduction in queues and stacks by adaptive bitwidth compression. 22-27
  
• Johan A. Pouwelse, Koen Langendoen, Henk J. Sips:
  Energy priority scheduling for variable voltage processors. 28-33
  
• Chaeseok Im, Huiseok Kim, Soonhoi Ha:
  Dynamic voltage scheduling technique for low-power multimedia applications using buffers. 34-39
  
• Han-Saem Yun, Jihong Kim:
  Power-aware modulo scheduling for high-performance VLIW processors. 40-45
  
• Flavius Gruian:
  Hard real-time scheduling for low-energy using stochastic data and DVS processors. 46-51
  
• Dejan Markovic, Borivoje Nikolic, Robert W. Brodersen:
  Analysis and design of low-energy flip-flops. 52-55
  
• Hoang Q. Dao, Kevin J. Nowka, Vojin G. Oklobdzija:
  Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation. 56-59
  
• Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali:
  Power-aware partitioned cache architectures. 64-67
  
• Atila Alvandpour, Ram Krishnamurthy, K. Soumyanath, Shekhar Borkar:
  A low-leakage dynamic multi-ported register file in 0.13mm CMOS. 68-71
  
• Jun Yang, Rajiv Gupta:
  Energy-efficient load and store reuse. 72-75
  
• Mahmut T. Kandemir, J. Ramanujam, Ugur Sezer:
  Compiler support for block buffering. 76-79
  
• Eui-Young Chung, Luca Benini, Giovanni De Micheli:
  Automatic source code specialization for energy reduction. 80-83
  
• Jun Yang, Rajiv Gupta:
  FV encoding for low-power data I/O. 84-87
  
• Daler N. Rakhmatov, Sarma B. K. Vrudhula:
  Time-to-failure estimation for batteries in portable electronic systems. 88-91
  
• Vlasios Tsiatsis, Scott Zimbeck, Mani B. Srivastava:
  Architecture strategies for energy-efficient packet forwarding in wireless sensor networks. 92-95
  
• Curt Schurgers, Olivier Aberthorne, Mani B. Srivastava:
  Modulation scaling for Energy Aware Communication Systems. 96-99
  
• Christian Belady:
  Cooling and power consideration for semiconductors into the next century. 100-105
  
• Andrew Wang, Seong-Hwan Cho, Charles Sodini, Anantha Chandrakasan:
  Energy efficient Modulation and MAC for Asymmetric RF Microsensor Systems. 106-111
  
• Song Ye, Koji Yano, C. Andre T. Salama:
  1 V, 1.9 GHz mixer using a lateral bipolar transistor in CMOS. 112-116
  
• Mohamed Mostafa, Sherif H. K. Embabi, Mostafa Elmala:
  A 60dB, 246MHz CMOS variable gain amplifier for subsampling GSM receivers. 117-122
  
• Hyunsik Im, T. Inukai, H. Gomyo, T. Hiramoto, T. Sakurai:
  VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. 123-128
  
• Xiaobo Fan, Carla Schlatter Ellis, Alvin R. Lebeck:
  Memory controller policies for DRAM power management. 129-134
  
• Russ Joseph, Margaret Martonosi:
  Run-time power estimation in high performance microprocessors. 135-140
  
• Phillip Stanley-Marbell, Michael S. Hsiao:
  Fast, flexible, cycle-accurate energy estimation. 141-146
  
• James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De:
  Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. 147-152
  
• Joong-Seok Moon, William C. Athas, Peter A. Beerel:
  Theory and practical implementation of harmonic resonant rail driver. 153-158
  
• Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou:
  A resonant clock generator for single-phase adiabatic systems. 159-164
  
• Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown:
  Enchanced multi-threshold (MTCMOS) circuits using variable well bias. 165-169
  
• Alessandro Bogliolo:
  Encodings for high-performance for energy-efficient signaling. 170-175
  
• Luca Macchiarulo, Enrico Macii, Massimo Poncino:
  Low-energy for deep-submicron address buses. 176-181
  
• Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram:
  Irredundant address bus encoding for low power. 182-187
  
• Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil Dutt:
  Low power address encoding using self-organizing lists. 188-193
  
• Deborah Estrin:
  Wireless sensor networks: application driver for low power distributed systems. 194
  
• Siva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan, Shekhar Borkar:
  Scaling of stack effect and its application for leakage reduction. 195-200
  
• Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai:
  Variable threshold CMOS (VTCMOS) in series connected circuits. 201-206
  
• Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De:
  Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. 207-212
  
• Rongtian Zhang, Kaushik Roy, David B. Janes:
  Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design. 213-218
  
• Frank Vahid, Ann Gordon-Ross:
  A self-optimizing embedded microprocessor using a loop table for low power. 219-224
  
• Daehong Kim, Dongwan Shin, Kiyoung Choi:
  Low power pipelining of linear systems: a common operand centric approach. 225-230
  
• Yun Cao, Hiroto Yasuura:
  A system-level energy minimization approach using datapath width optimization. 231-236
  
• Gurhan Kucuk, Kanad Ghose, Dmitry Ponomarev, Peter M. Kogge:
  Energy: efficient instruction dispatch buffer design for superscalar processors. 237-242
  
• Tirdad Sowlati, Vickram Vathulya, Domine Leenaerts:
  High density capacitance structures in submicron CMOS for low power RF application. 243-246
  
• Ahmed Mostafa, Mourad N. El-Gamal:
  A CMOS VCO architecture suitable for sub-1 volt high-frequency (8.7-10 GHz) RF applications. 247-250
  
• Charles Chien, Igor Elgorriaga, Charles McConaghy:
  Low-power direct-sequence spread-spectrum modem architecture for distributed wireless sensor networks. 251-254
  
• Vjekoslav Svilan, James B. Burr, G. Tyler:
  Effects of elevated temperature on tunable near-zero threshold CMOS. 255-258
  
• Koji Fujii, Takakuni Douseki, Yuichi Kado:
  A sub-1V dual-threshold domino circuit using product-of-sum logic. 259-262
  
• W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi:
  Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. 263-266
  
• Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy:
  Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. 267-270
  
• Dongkun Shin, Jihong Kim:
  A profile-based energy-efficient intra-task voltage scheduling algorithm for real-time applications. 271-274
  
• Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao:
  Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessors. 275-278
  
• Ali Manzak, Chaitali Chakrabarti:
  Variable voltage task scheduling algorithms for minimizing energy. 279-282
  
• Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai:
  Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. 283-286
  
• Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni:
  Synthesis of low-leakage PD-SOI circuits with body-biasing. 287-290
  
• Rob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone:
  Low-power technology mapping for mixed-swing logic. 291-294
  
• Srinivas Bodapati, Farid N. Najm:
  Frequency-domain supply current macro-model. 295-298
  
• Rola A. Baki, Mourad N. El-Gamal:
  A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding. 299-304
  
• Takeshi Fukumoto, Hiroyuki Okada, Kazuyuki Nakamura:
  Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operations. 305-309
  
• Louis S. Y. Wong, Shohan Hossain, Andre Walker:
  Leakage current cancellation technique for low power switched-capacitor circuits. 310-315
  
• Kwang-Bo Cho, Alexander Krymski, Eric R. Fossum:
  A 3-pin 1.5 V 550 mW 176 x 144 self-clocked CMOS active pixel image sensor. 316-321
  
• Luca Benini, Alberto Macii, Alberto Nannarelli:
  Cached-code compression for energy minimization in embedded processors. 322-327
  
• David Garrett, Bing Xu, Chris Nicol:
  Energy efficient turbo decoding for 3G mobile. 328-333
  
• Lei Wang, Naresh R. Shanbhag:
  Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. 334-339
  
• Emil Talpes, Diana Marculescu:
  Power reduction through work reuse. 340-345
  
• Victor V. Zyuban, D. Meltzer:
  Clocking strategies and scannable latches for low power appliacations. 346-351
  
• Hyung-il Kim, Kaushik Roy:
  Ultra-low power DLMS adaptive filter for hearing aid applications. 352-357
  
• Seiji Miura, Kazushige Ayukawa, Takao Watanabe:
  A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. 358-363
  
• Paul-Peter Sotiriadis, Theodoros Konstantakopoulos, Anantha Chandrakasan:
  Analysis and implementation of charge recycling for deep sub-micron buses. 364-369
  
• Youngsoo Shin, Takayasu Sakurai:
  Estimation of power distribution in VLSI interconnects. 370-375
  
• Sudhakar Bobba, Ibrahim N. Hajj:
  Maximum voltage variation in the power distribution network of VLSI circuits with RLC models. 376-381
  
• Sung Park, Andreas Savvides, Mani B. Srivastava:
  Battery capacity measurement and analysis using lithium coin cell battery. 382-387
  
• Rajendran Panda, Savithri Sundareswaran, David Blaauw:
  On the interaction of power distribution network with substrate. 388-393
  

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