ISLPED 2000: Rapallo, Italy

@proceedings{DBLP:conf/islped/2000,
  editor    = {David Blaauw and
               Christian C. Enz and
               Thaddeus Gabara and
               Enrico Macii},
  title     = {Proceedings of the 2000 International Symposium on Low Power
               Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000},
  booktitle = {ISLPED},
  publisher = {ACM},
  year      = {2000},
  isbn      = {1-58113-190-9},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Khalil Najafi:
  Low-power micromachined microsystems (invited talk). 1-8
  
• Thomas D. Burd, Robert W. Brodersen:
  Design issues for dynamic voltage scaling. 9-14
  
• Nicola Dragone, Akshay Aggarwal, L. Richard Carley:
  An adaptive on-chip voltage regulation technique for low-power applications. 20-24
  
• Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
  Robust ultra-low power sub-threshold DTMOS logic. 25-30
  
• Amit Sinha, Alice Wang, Anantha Chandrakasan:
  Algorithmic transforms for efficient energy scalable computation. 31-36
  
• Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli:
  Operating-system directed power reduction. 37-42
  
• Gang Qu, Miodrag Potkonjak:
  Energy minimization with guaranteed quality of service. 43-49
  
• Tajana Simunic, Haris Vikalo, Peter W. Glynn, Giovanni De Micheli:
  Energy efficient design of portable wireless systems. 49-54
  
• P. Cusinato, F. Stefani, A. Baschirotto:
  Power consumption reduction in high-speed Sigma-Delta bandpass modulators. 55-60
  
• Mattias Duppils, Christer Svensson:
  Low power mixed analog-digital signal processing. 61-66
  
• Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti:
  A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers. 67-72
  
• Silvio Bolliri, Paolo Porcu, Luigi Raffo:
  A micro-power mixed signal IC for battery-operated burglar alarm systems. 73-77
  
• Luca Benini, Alberto Macii, Massimo Poncino:
  A recursive algorithm for low-power memory partitioning. 78-83
  
• Victor V. Zyuban, Peter M. Kogge:
  Optimization of high-performance superscalar architectures for energy efficiency. 84-89
  
• Trevor Pering, Thomas D. Burd, Robert W. Brodersen:
  Voltage scheduling in the IpARM microprocessor system. 96-101
  
• Jason M. Musicer, Jan M. Rabaey:
  MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments. 102-107
  
• Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
  Noise-aware power optimization for on-chip interconnect. 108-113
  
• Antonio G. M. Strollo, Ettore Napoli, Davide De Caro:
  New clock-gating techniques for low-power flip-flops. 114-119
  
• Tudor Vinereanu, Sverre Lidholm:
  An improved pass transistor synthesis method for low power, high speed CMOS circuits. 120-124
  
• Gang Qu, Miodrag Potkonjak:
  Achieving utility arbitrarily close to the optimal with limited energy. 125-130
  
• Junghwan Choi, Jinhwan Jeon, Kiyoung Choi:
  Power minimization of functional units partially guarded computation. 131-136
  
• Erik Brockmeyer, Arnout Vandecappelle, Francky Catthoor:
  Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications. 137-142
  
• Xunwei Wu, Massoud Pedram:
  Low power sequential circuit design by using priority encoding and clock gating. 143-148
  
• Giovanni De Micheli, Tony Correale, Pietro Erratico, Srini Raghvendra, Hugo De Man, Jerry Frankil, Vivek Tiwari:
  Do our low-power tools have enough horse power? (panel session) (title only). 149
  
• Sven Mattisson:
  Low-power considerations in the design of bluetooth (invited talk). 151-154
  
• Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry:
  High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies. 155-160
  
• Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae:
  A three-port nRERL register file for ultra-low-energy applications. 161-166
  
• Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl:
  Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. 167-172
  
• William C. Athas:
  Practical considerations of clock-powered logic. 173-178
  
• Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju:
  Model and analysis for combined package and on-chip power grid simulation. 179-184
  
• Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee:
  Cycle-accurate energy consumption measurement and analysis: case study of ARM7TDMI. 185-190
  
• Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan:
  Speeding up power estimation of embedded software. 191-196
  
• Kavel M. Büyüksahin, Farid N. Najm:
  High-level power estimation with interconnect effects. 197-202
  
• Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang:
  "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). 203-206
  
• Sandeep Dhar, Dragan Maksimovic:
  Low-power digital filtering using multiple voltage distribution and adaptive voltage scaling (poster session). 207-209
  
• Jae-Hee Won, Kiyoung Choi:
  Low power self-timed Radix-2 division (poster session). 210-212
  
• Lama H. Chandrasena, Michael J. Liebelt:
  A rate selection algorithm for quantized undithered dynamic supply voltage scaling (poster session). 213-215
  
• Andrea Gerosa, Arianna Novo, Andrea Neviani:
  Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session). 216-218
  
• Friedel Gerfers, Yiannos Manoli:
  A 1.5V low-power third order continuous-time lowpass Sigma-Delta A/D converter (poster session). 219-221
  
• Chunlei Shi, Yue Wu, Mohammed Ismail:
  Design of a low-power CMOS baseband circuit for wideband CDMA testbed (poster session). 222-224
  
• Carl James Debono, Franco Maloberti, Joseph Micallef:
  A low-voltage CMOS multiplier for RF applications (poster session). 225-227
  
• Koichi Nose, Soo-Ik Chae, Takayasu Sakurai:
  Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). 228-230
  
• Kanad Ghose:
  Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session). 231-233
  
• Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
  Low power synthesis of sum-of-products computation (poster session). 234-237
  
• Andrea Acquaviva, Riccardo Scarsi:
  A spatially-adaptive bus interface for low-switching communication (poster session). 238-240
  
• Afzal Malik, Bill Moyer, Dan Cermak:
  A low power unified cache architecture providing power and performance flexibility (poster session). 241-243
  
• G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
  Memory system energy (poster session): influence of hardware-software optimizations. 244-246
  
• Sathishkumar Udayanarayanan, Chaitali Chakrabarti:
  Energy-efficient code generation for DSP56000 family (poster session). 247-249
  
• Wei-Chung Cheng, Massoud Pedram:
  Power-optimal encoding for DRAM address bus (poster session). 250-252
  
• Diana Marculescu:
  Profile-driven code execution for low power dissipation (poster session). 253-255
  
• Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong:
  An asynchronous matrix-vector multiplier for discrete cosine transform. 256-261
  
• Khurram Muhammad, Robert B. Staszewski, Poras T. Balsara:
  Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. 262-267
  
• Vjekoslav Svilan, Masataka Matsui, James B. Burr:
  Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS. 268-272
  
• Alain-Serge Porret, Thierry Melly, Eric A. Vittoz, Christian C. Enz:
  Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process. 273-278
  
• Francesco Svelto, S. Deantoni, G. Montagna, Rinaldo Castello:
  An 8mA, 3.8dB NF, 40dB gain CMOS front-end for GPS applications. 279-283
  
• Tirdad Sowlati, Sifen Luo:
  Bias boosting technique for a 1.9GHz class AB RF amplifier. 284-288
  
• Liang Dai, Ramesh Harjani:
  Analysis and design of low-phase-noise ring oscillators. 289-294
  
• Naresh R. Shanbhag, K. Soumyanath, Samuel Martin:
  Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). 295-302
  
• Ingrid Verbauwhede, Chris Nicol:
  Low power DSP's for wireless communications (embedded tutorial session). 303-310
  

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