ISLPED 1998: Monterey, California, USA

@proceedings{DBLP:conf/islped/1998,
  editor    = {Anantha Chandrakasan and
               Sayfe Kiaei},
  title     = {Proceedings of the 1998 International Symposium on Low Power
               Electronics and Design, 1998, Monterey, California, USA, August
               10-12, 1998},
  booktitle = {ISLPED},
  publisher = {ACM},
  year      = {1998},
  isbn      = {1-58113-059-7},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Bryan D. Ackland, Chris Nicol:
  High performance DSPs - what's hot and what's not? 1-6
  
• Christer Svensson, Atila Alvandpour:
  Low power and low voltage CMOS digital circuit techniques. 7-10
  
• Tsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser:
  CMOS front end components for micropower RF wireless systems. 11-15
  
• Tamara I. Ahrens, Thomas H. Lee:
  A 1.4-GHz 3-mW CMOS LC low phase noise VCO using tapped bond wire inductances. 16-19
  
• Herbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost:
  A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology. 20-23
  
• Chun-hong Chen, Chi-Ying Tsui:
  Towards the capability of providing power-area-delay trade-off at the register transfer level. 24-29
  
• Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
  Stream synthesis for efficient power simulation based on spectral transforms. 30-35
  
• Diana Marculescu, Radu Marculescu, Massoud Pedram:
  Theoretical bounds for switching activity analysis in finite-state machines. 36-41
  
• Eric Y. Chou, A. J. Budrys, Kit M. Cham:
  Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture. 42-47
  
• Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi:
  A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. 48-53
  
• S. J. Abou-Samra, P. A. Aisa, Alain Guyot, Bernard Courtois:
  3D CMOS SOL for high performance computing. 54-58
  
• Joonho Gil, Minkyu Je, Jongho Lee, Hyungcheol Shin:
  A high speed and low power SOL inverter using active body-bias. 59-63
  
• R. Iris Bahar, Gianluca Albera, Srilatha Manne:
  Power and performance tradeoffs using various caching strategies. 64-69
  
• Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos:
  Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. 70-75
  
• Trevor Pering, Thomas D. Burd, Robert W. Brodersen:
  The simulation and evaluation of dynamic voltage scaling algorithms. 76-81
  
• Taku Ohsawa, Koji Kai, Kazuaki Murakami:
  Optimizing the DRAM refresh count for merged DRAM/logic LSIs. 82-87
  
• Ferdinand Sluijs, Kees Hart, Wouter Groeneveld, Stephan Haag:
  Integrated DC/DC converter with digital controller. 88-90
  
• Rafael J. Betancourt-Zamora, Thomas H. Lee:
  CMOS VCOs for frequency synthesis in wireless biotelemetry. 91-94
  
• Gareth Keane, Jonathan Spanier, Roger Woods:
  The impact of data characteristics and hardware topology on hardware selection for low power DSP. 94-96
  
• Mircea R. Stan:
  Low threshold CMOS circuits with low standby current. 97-99
  
• Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl:
  Minimum supply voltage for bulk Si CMOS GSI. 100-102
  
• Volker Dudek, Reinhard Grube, Bernd Höfflinger, Michael Schau:
  0.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology. 103-105
  
• L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy:
  Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits. 106-108
  
• Alberto Nannarelli, Tomás Lang:
  Power-delay tradeoffs for radix-4 and radix-8 dividers. 109-111
  
• Mauro Chinosi, Roberto Zafalon, Carlo Guardiani:
  Automatic characterization and modeling of power consumption in static RAMs. 112-114
  
• Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram:
  Improving sampling efficiency for system level power estimation. 115-117
  
• Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano:
  Power invariant vector compaction based on bit clustering and temporal partitioning. 118-120
  
• Catherine H. Gebotys, Robert J. Gebotys:
  An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. 121-123
  
• Jay Abraham:
  Power calculation and modeling in deep submicron. 124-126
  
• Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi:
  Partial bus-invert coding for power optimization of system level bus. 127-129
  
• Rafael Peset Llopis, Kees G. W. Goossens:
  The petrol approach to high-level power estimation. 130-132
  
• Won Namgoong, Teresa H. Y. Meng:
  Power consumption of parallel spread spectrum correlator architectures. 133-135
  
• Uzi Zangi, Ran Ginosar:
  A low power video processor. 136-138
  
• Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
  Power dissipated by CMOS gates driving lossless transmission lines. 139-142
  
• David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards:
  Emerging power management tools for processor design. 143-148
  
• Jacques C. Rudell, Jia-Jiunn Ou, R. Sekhar Narayanaswami, George Chien, Jeffrey A. Weldon, Li Lin, King-Chun Tsai, Luns Tee, Kelvin Khoo, Danelle Au, Troy Robinson, Danilo Gerna, Masanori Otsuka, Paul R. Gray:
  Recent developments in high integration multi-standard CMOS transceivers for personal communication systems. 149-154
  
• Eric Kusse, Jan M. Rabaey:
  Low-energy embedded FPGA structures. 155-160
  
• Hui Zhang, Jan M. Rabaey:
  Low-swing interconnect interface circuits. 161-166
  
• Suhwan Kim, Marios C. Papaefthymiou:
  True single-phase energy-recovering logic for low-power, high-speed VLSI. 167-172
  
• Luca Benini, Robin Hodgson, Polly Siegel:
  System-level power estimation and optimization. 173-178
  
• Sari L. Coumeri, Donald E. Thomas:
  Memory modeling for system synthesis. 179-184
  
• Luca Benini, Alessandro Bogliolo, Stefano Cavallucci, Bruno Riccò:
  Monitoring system activity for OS-directed dynamic power management. 185-190
  
• Abram P. Dancy, Anantha Chandrakasan:
  A reconfigurable dual output low power digital PWM power converter. 191-196
  
• Tohru Ishihara, Hiroto Yasuura:
  Voltage scheduling problem for dynamically variable voltage processors. 197-202
  
• Thomas Burger, Qiuting Huang:
  On the optimum design of regulated cascode operational transconductance amplifiers. 203-208
  
• Unni Narayanan, Peichen Pan, C. L. Liu:
  Low power logic synthesis under a general delay model. 209-214
  
• Ki-Seok Chung, C. L. Liu:
  Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. 215-220
  
• Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
  A power optimization method considering glitch reduction by gate sizing. 221-226
  
• Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa:
  A unified approach in the analysis of latches and flip-flops for low-power systems. 227-232
  
• Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng:
  Estimation of maximum power supply noise for deep sub-micron designs. 233-238
  
• Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy:
  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. 239-244
  
• Atila Alvandpour, Per Larsson-Edefors, Christer Svensson:
  Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. 245-249
  
• Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
  Decorrelating (DECOR) transformations for low-power adaptive filters. 250-255
  
• John R. Sacha, Mary Jane Irwin:
  The logarithmic number system for strength reduction in adaptive filtering. 256-261
  
• David Garrett, Mircea R. Stan:
  Low power architecture of the soft-output Viterbi algorithm. 262-267
  
• J. Patrick Brennan, Alvar Dean, Stephan Kenyon, Sebastian Ventrone:
  Low power methodology and design techniques for processor design. 268-273
  
• Michael Benoit, Sandy Taylor, David Overhauser, Steffen Rochel:
  Power distribution in high-performance design. 274-278
  
• Michael Bolotski, Phillip Alvelda:
  Low-power miniaturized information display systems. 279-281
  
• Jinn-Shyan Wang, Po-Hui Yang, Wayne Tseng:
  Low-power embedded SRAM macros with current-mode read/write operations. 282-287
  
• Stephan Avery, Marwan A. Jabri:
  A three-port adiabatic register file suitable for embedded applications. 288-292
  
• Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano:
  A low power SRAM using auto-backgate-controlled MT-CMOS. 293-298
  
• Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
  Fast high-level power estimation for control-flow intensive design. 299-304
  
• Victor V. Zyuban, Peter M. Kogge:
  The energy complexity of register files. 305-310
  
• Julio Leao da Silva Jr., Francky Catthoor, Diederik Verkest, Hugo De Man:
  Power exploration for dynamic data types through virtual memory management refinement. 311-316
  

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