ISCAS 2004: Vancouver, BC, Canada - Volume 2
Deepa Kundur, Yang Zhao, Patrizio Campisi: A stenographic framework for dual authentication and compression of high resolution imagery. 1-4- Azadeh Kushki, Panagiotis Androutsos, Konstantinos N. Plataniotis, Anastasios N. Venetsanopoulos: A unified framework for similarity calculation between images. 9-12
- Bong-Ho Lee, So Ra Park, Young Kwon Hahm, Soo In Lee: An efficient transmission framework of digital multimedia broadcasting (DMB) systems. 13-16
- Qiang Liu, Jenq-Neng Hwang: A scalable video transmission system using bandwidth inference in congestion control. 17-20
- Guorong Xuan, Yun Q. Shi, Zhicheng Ni, Jidong Chen, Chengyun Yang, Yizhan Zhen, Junxiang Zheng: High capacity lossless data hiding based on integer wavelet transform. 29-32
- Yun Q. Shi, Zhicheng Ni, Dekun Zou, Changyin Liang, Guorong Xuan: Lossless data hiding: fundamentals, algorithms and applications. 33-36
- Anthony T. S. Ho, Niladri B. Puhan, Pina Marziliano, Anamitra Makur, Yong Liang Guan: Perception based binary image watermarking. 37-40
- Wei Jiang, Mingjing Li, HongJiang Zhang, Jie Zhou: Relevance feedback using random subspace method. 41-44
- Tahir Amin, Ling Guan: Interactive content-based image retrieval using Laplacian mixture model in the wavelet domain. 45-48
- Sang Hyun Kim, Rae-Hong Park: A novel approach to video sequence matching using color and edge features with the modified Hausdorff distance. 57-60
- Keman Yu, Jiang Li, Shipeng Li: A novel approach to real time multimedia forwarding over heterogeneous networks. 61-64
- Hsiao-Cheng Wei, Yuh-Chou Tsai, Chia-Wen Lin: Prioritized retransmission for error protection of video streaming over WLANs. 65-68
- Bontae Koo, Jinkyu Kim, Juhyun Lee, Nak-Woong Eum, Jongdae Kim, Hyunmook Cho: Channel decoder architecture of OFDM based DMB system. 73-76
- Ching-Ho Chen, Chun-Jen Tsai: Out-of-loop rate control for video codec hardware/software co-design. 85-88
- Naoki Nitanda, Miki Haseyama, Hideo Kitajima: An audio-scene cut detection method using fuzzy c-means algorithm for audio-visual indexing. 89-92
- Ming-Chieh Chi, Mei-Juan Chen, Ching-Ting Hsu: Region-of-Interest video coding by fuzzy control for H.263+ standard. 93-96
- Ko-Cheung Hui, Wan-Chi Siu, Yui-Lam Chan: New adaptive partial distortion search using clustered pixel matching error characteristic. 97-100
- Shi-Lin Wang, Wing Hong Lau, Shu Hung Leung, H. Yan: A real-time automatic lipreading system. 101-104
- Guang Dai, Yuntao Qian: Face recognition with the robust feature extracted by the generalized Foley-Sammon transform. 109-112
- Cenk Demiroglu, David V. Anderson: Two-sensor noise robust ASR with missing frames for Aurora2 task. 113-116
- Rastislav Lukac, Konstantinos N. Plataniotis: A new CFA interpolation technique for single-sensor digital cameras. 121-124
- Nelson Yen-Chung Chang, Kun-Bin Lee, Chein-Wei Jen: Trace-path analysis and performance estimation for multimedia application in embedded system. 129-132
- Jinghong Zheng, Lap-Pui Chau: A temporal error concealment algorithm for H.264 using Lagrange interpolation. 133-136
- Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen: A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. 141-144
- Hae-Yong Kang, Kyung-Ah Jeong, Jung-Yang Bae, Young-Su Lee, Seung-Ho Lee: MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller. 145-148
- Yueh-Yi Wang, Yan-Tsung Peng, Chun-Jen Tsai: VLSI architecture design of motion estimator and in-loop filter for MPEG-4 AVC/H.264 encoders. 149-152
- Donghyun Kim, Lee-Sup Kim: Division-free rasterizer for perspective-correct texture filtering. 153-156
- Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Chi-Lung Wang: An adaptive DSP processor for high-efficiency computing MPEG-4 video encoder. 157-160
- Peter H. W. Wong, Andy Chang, Oscar C. Au: On improving the iterative watermark embedding technique for JPEG-to-JPEG watermarking. 161-164
- Chun-Shien Lu: On the security of structural information extraction/embedding for images. 169-172
- Jie Chen, Hongxun Yao, Wen Gao, Shaohui Liu: A robust watermarking method based on wavelet and Zernike transform. 173-176
- Yazhou Liu, Wen Gao, Hongxun Yao, Shaohui Liu: A texture-based tamper detection scheme by fragile watermark. 177-180
- Muhammad Waqas Bhatti, Yongjin Wang, Ling Guan: A neural network approach for human emotion recognition in speech. 181-184
- Shi Lu, Michael R. Lyu, Irwin King: Video summarization by spatial-temporal graph optimization. 197-200
- Lihang Ying, Anup Basu, Satish K. Tripathi: Multi-server optimal bandwidth monitoring for collaborative distributed retrieval. 201-204
- Dong Wang, Cedric Nishan Canagarajah, David W. Redmill, David R. Bull: Multiple description video coding based on zero padding. 205-208
- Kitae Nahm, C. C. Jay Kuo: Low-variance TCP-friendly throughput estimation for congestion control of layered video multicast. 209-212
- Ching-Ting Hsu, Mei-Juan Chen, Chin-Hui Huang: High performance spatial-temporal de-interlacing technique using interfield information. 213-216
- Jui-Cheng Yen, Hun-Chen Chen, Shin-Shian Jou: A new cryptographic system and its VLSI implementation. 221-224
- Bing-Fei Wu, Chung-Fu Lin: Analysis and architecture design for high performance JPEG2000 coprocessor. 225-228
- Mladen Panovic, Andreas Demosthenous: A compact block-matching cell for analogue motion estimation processors. 229-232
- Yeong-Kang Lai, Lien-Fei Chen: A performance-driven configurable motion estimator for full-search block-matching algorithm. 233-236
- Mohammed Sayed, Wael M. Badawy: A novel embedded memory architecture for real-time mesh-based motion estimation. 237-240
- Deepak N. Agarwal, Sumitkumar N. Pamnani, Gang Qu, Donald Yeung: Transferring performance gain from software prefetching to energy reduction. 241-244
- Andrea Gerosa, Andrea Neviani: A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter. 245-248
- Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou: Empirical evaluation of timing and power in resonant clock distribution. 249-252
- Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee: A power and area efficient multi-mode FEC processor. 253-256
- David J. Willingham, Izzet Kale: Asynchronous, quasi-Adiabatic (Asynchrobatic) logic for low-power very wide data width applications. 257-260
- Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima: A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level. 261-264
- Faycal Bensaali, Abbes Amira, Ahmed Bouridane: An efficient architecture for color space conversion using Distributed Arithmetic. 265-268
- Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen: Hardware architecture design for H.264/AVC intra frame coder. 269-272
- Tung-Chien Chen, Yu-Wen Huang, Liang-Gee Chen: Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture. 273-276
- Christoph Saas, Artur Wróblewski, Josef A. Nossek: Low-power DA-converters for display applications using stepwise charging and charge recovery. 277-280
- Henrik Eriksson, Per Larsson-Edefors: Glitch-conscious low-power design of arithmetic circuits. 281-284
- Tomoyuki Yamanaka, Vasily G. Moshnyaga: Reducing multiplier energy by data-driven voltage variation. 285-288
- Michael M. Yang, James A. Barby: A novel fast low voltage dynamic threshold true single phase clocking adiabatic circuit. 289-292
- Hafijur Rahman, Chaitali Chakrabarti: A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. 297-300
- Ching-Yeh Chen, Shao-Yi Chien, Wei-Min Chao, Yu-Wen Huang, Liang-Gee Chen: Hardware architecture for global motion estimation for MPEG-4 Advanced Simple Profile. 301-304
- Kun-Bin Lee, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen: QME: an efficient subsampling-based block matching algorithm for motion estimation. 305-308
- Arindam Basu, Ashis Kumar Mal, Anindya Sundar Dhar: Digital controlled analog architecture for DCT and DST using capacitor switching. 309-312
- Siou-Shen Lin, Po-Chih Tseng, Liang-Gee Chen: Low-power parallel tree architecture for full search block-matching motion estimation. 313-316
- Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen: A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding. 317-320
- Siu-Kei Wong, Chi-Ying Tsui: Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus. 321-324
- Tien-Fu Chen, Tsung-Ming Hsieh, Chun-Li Wei: Unified bus encoding by stream reconstruction with variable strides. 329-332
- Abdullah Mamun, Rajendra S. Katti: A new parallel architecture for low power linear feedback shift registers. 333-336
- Yu-Lin Chang, Shyh-Feng Lin, Liang-Gee Chen: Extended intelligent edge-based line average with its implementation and test method. 341-344
- Amine Bermak, Farid Boussaïd, Abdesselam Bouzerdoum: A low power current-mode pixel with on-chip FPN cancellation and digital shutter. 345-348
- Hideo Yamasaki, Tadashi Shibata: A real-time VLSI median filter employing two-dimensional bit-propagating architecture. 349-352
- Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen: Reconfigurable discrete cosine transform processor for object-based video signal processing. 353-356
- Sven Simon, Matthias Müller, Holger Gryska, Andreas Wortmann, Steffen Buch: An instruction set for the efficient implementation of the CORDIC algorithm. 357-360
- Kimish Patel, Enrico Macii, Massimo Poncino: Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip. 361-364
- Rajendra S. Katti, Xiaoyu Ruan: Left-to-right binary signed-digit recoding for elliptic curve cryptography. 365-368
- Yuejian Wu: Low power decoding of BCH codes. 369-372
- Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Haque, Ahsan Raja Chowdhury: A heuristic approach to synthesize Boolean functions using TANT network. 373-376
- Mario Steinert, Stefano Marsili: Power consumption optimization for low latency Viterbi Decoder. 377-380
- Hyun-Yong Lee, In-Cheol Park: A fast Reed-Solomon Product-Code decoder without redundant computations. 381-384
- Sung Dae Kim, Sug Hyun Jeong, Myung Hoon Sunwoo, Kyung Ho Kim: Novel bit manipulation unit for communication digital signal processors. 385-388
- Hao Zhong, Tong Zhang: Joint code-encoder-decoder design for LDPC coding system VLSI implementation. 389-392
- Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang: Multi-level memory systems using error control codes. 393-396
- Se-Hyeon Kang, In-Cheol Park: Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. 397-400
- Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh: Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. 401-404
- Masaaki Iijima, Katsuya Fujita, Kazuki Fukuoka, Masahiro Numa, Keisuke Yamamoto, Kengo Takata: A technique for high-speed circuits on SOI using look-ahead type active body bias control. 405-408
- Baohua Wang, Pinaki Mazumder: Fast thermal analysis for VLSI circuits via semi-analytical Green's function in multi-layer materials. 409-412
- Volkan Kursun, Eby G. Friedman: Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. 417-420
- Christophe Layer, Hans-Jörg Pfleiderer, Christoph Heer: A scalable compact architecture for the computation of integer binary logarithms through linear approximation. 421-424
- Magnus Karlsson, Mark Vesterbacka, Wlodek Kulesza: A method for increasing the throughput of fixed coefficient digit-serial/parallel multipliers. 425-428
- Shaoqiang Bi, Wei Wang, Asim J. Al-Khalili: Modulo deflation in (2n+1, 2n, 2n-1) converters. 429-432
- Mark G. Arnold: Geometric-mean interpolation for logarithmic number systems. 433-436
- Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang: A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders. 437-440
- Aydin O. Balkan, Gang Qu, Uzi Vishkin: Arbitrate-and-move primitives for high throughput on-chip interconnection networks. 441-444
- Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang: Substrate noise-aware floorplanning for mixed-signal SOCs. 445-448
- Taek-Jun Kwon, Joong-Seok Moon, Jeff Sondeen, Jeffrey T. Draper: A 0.18 µm implementation of a floating-point unit for a processing-in-memory system. 453-456
- Aleksandar Pance, Madan Mohan, Paul Master: Power-aware implementation of ASIC/SOC in 0.13 micron CMOS technology. 457-460
- Henrik Eriksson, Per Larsson-Edefors: Dynamic pass-transistor dot operators for efficient parallel-prefix adders. 461-464
- Massimo Alioto, Gaetano Palumbo, Massimo Poli: A gate-level strategy to design Carry Select Adders. 465-468
- Kenny Johansson, Oscar Gustafsson, Lars Wanhammar: Switching activity in bit-serial constant-coefficient multipliers. 469-472
- Oscar Gustafsson, Andrew G. Dempster, Lars Wanhammar: Multiplier blocks using carry-save adders. 473-476
- Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka: A low latency and low power dynamic Carry Save Adder. 477-480
- Edgar F. M. Albuquerque, Manuel M. Silva: An experimental comparison of substrate noise generated by CMOS and by low-noise digital circuits. 481-484
- Husni M. Habal, Terri S. Fiez, Kartikeya Mayaram: An accurate and efficient estimation of switching noise in synchronous digital circuits. 485-488
- Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac Vilela: An improved technique to increase noise-tolerance in dynamic digital circuits. 489-492
- Fernando Mendoza-Hernandez, Mónico Linares Aranda, Víctor H. Champac Vilela: The noise immunity of dynamic digital circuits with technology scaling. 493-496
- Omar Hafiz, Pinhong Chen, Janet Meiling Wang: A new non-iterative model for switching window computation with crosstalk noise. 497-500
- Keshab K. Parhi: Novel pipelining of MSB-first add-compare select unit structure for Viterbi decoders. 501-504
- Ruwan N. S. Ratnayake, Gu-Yeon Wei, Aleksandar Kavcic: Pipelined parallel architecture for high throughput MAP detectors. 505-508
- Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo: VLSI architecture exploration for sliding-window Log-MAP decoders. 513-516
- Wing-Kin Chan, Chiu-sing Choy, Cheong-fat Chan, Kong-Pang Pun: An asynchronous SOVA decoder for wireless communication application. 517-520
- Junmou Zhang, Eby G. Friedman: Decoupling technique and crosstalk analysis for coupled RLC interconnects. 521-524
- Maged Ghoneima, Yehea I. Ismail: Effect of relative delay on the dissipated energy in coupled interconnects. 525-528
- Junmou Zhang, Eby G. Friedman: Effect of shield insertion on reducing crosstalk noise between coupled interconnects. 529-532
- Anand Pappu, Alyssa B. Apsel: Electrical isolation and fanout in intra-chip optical interconnects. 533-536
- Bassel Soudan: Managing inductive coupling in wide signal busses. 537-40
- Refik Sever, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar: A high speed ASIC implementation of the Rijndael algorithm. 541-544
- Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner: Design of a reconfigurable AES encryption/decryption engine for mobile terminals. 545-548
- Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou: High-speed hardware implementations of the KASUMI block cipher. 549-552
- Nick A. Moldovyan, Ma A. Eremeev, Nicolas Sklavos, Odysseas G. Koufopavlou: New class of the FPGA efficient cryptographic primitives. 553-556
- Soner Yesil, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar: Two fast RSA implementations using high-radix montgomery algorithm. 557-560
- Shih-Lun Chen, Ming-Dou Ker: A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals. 573-576
- Che-Hao Chuang, Ming-Dou Ker: Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology. 577-580
- Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk: Autonomous Memory Block for reconfigurable computing. 581-584
- Volnei A. Pedroni: Compact Hamming-Comparator-based rank order filter for digital VLSI and FPGA implementations. 585-588
- Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler, David V. Anderson: Application performance of elements in a floating-gate FPAA. 589-592
- Pei-Yung Hsiao, Chun-Ho Hua, Chien-Chen Lin: A novel FPGA architectural implementation of pipelined thinning algorithm. 593-596
- Shuenn-Shyang Wang, Wan-Sheng Ni: An efficient FPGA implementation of advanced encryption standard algorithm. 597-600
- Magdy A. El-Moursy, Eby G. Friedman: Exponentially tapered H-tree clock distribution networks. 601-604
- Behzad Mesgarzadeh, Christer Svensson, Atila Alvandpour: A new mesochronous clocking scheme for synchronization in SoC. 605-608
- Matthias Müller, Andreas Wortmann, Sven Simon, Michael Kugel, Tim Schoenauer: The impact of clock gating schemes on the power dissipation of synthesizable register files. 609-612
- Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada: Leakage power reduction for clock gating scheme on PD-SOI. 613-616
- Baris Taskin, Ivan S. Kourtev: Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. 617-620
- Ming-Chih Hsieh, Zheng-Hong Wang, Hongchin Lin, Yen-Tai Lin: A new dual pumping circuit without body effects for low supply voltage. 621-624
- Ferdinando Bedeschi, Edoardo Bonizzoni, Osama Khouri, Claudio Resta, Guido Torelli: A fully symmetrical sense amplifier for non-volatile memories. 625-608
- Kuo-Hsing Cheng, Chia-Hung Wei, Shu-Yu Jiang: Static divided word matching line for low-power Content Addressable Memory design. 629-632
- Anna Labbé, Annie Pérez, Jean Michel Portal: Efficient hardware implementation of a CRYPTO-MEMORY based on AES algorithm and SRAM architecture. 637-640
- Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli: Positive-Feedback Source-Coupled Logic: a delay model. 641-644
- Tin Wai Kwan, Maitham Shams: Multi-GHz energy-efficient asynchronous pipelined circuits in MOS Current Mode Logic. 645-648
- Shahnam Khabiri, Maitham Shams: Implementation of MCML universal logic gate for 10 GHz-range in 0.13 µm CMOS technology. 653-656
- Alessandro Cabrini, Rino Micheloni, Osama Khouri, Stefano Gregori, Guido Torelli: High input range sense comparator for multilevel Flash memories. 657-660
- Yu-Yin Sung, Robert C. Chang: A novel CMOS double-edge triggered flip-flop for low-power applications. 665-668
- Peiyi Zhao, Pradeep Kumar Golconda, Magdy Bayoumi: Contention reduced/conditional discharge flip-flops for level conversion in CVS systems. 669-672
- Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner: An efficient implementation of D-Flip-Flop using the GDI technique. 673-676
- Mohammad H. Tehranipour, Mehrdad Nourani, Karim Arabi, Ali Afzali-Kusha: Mixed RL-Huffman encoding for power reduction and data compression in scan test. 681-684
- Kevin Peterson, Yvon Savaria: Assertion-based on-line verification and debug environment for complex hardware systems. 685-688
- Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani: Low power pattern generation for BIST architecture. 689-692
- Sangjin Hong, Miodrag Bolic, Petar M. Djuric: A design complexity comparison method for loop-based signal processing algorithms: particle filters. 693-696
- Isa Servan Uzun, Abbes Amira, Ahmed Bouridane: An efficient architecture for 1-D discrete biorthogonal wavelet transform. 697-700
- Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, An-Yeu Wu: Least squares approximation-based ROM-free direct digital frequency synthesizer. 701-704
- Malinky Ghosh, Lakshmi S. J. Chimakurthy, Foster F. Dai, Richard C. Jaeger: A novel DDS architecture using nonlinear ROM addressing with improved compression ratio and quantisation noise. 705-708
- Sung-Won Lee, In-Cheol Park: Quadrature direct digital frequency synthesis using fine-grain angle rotation. 709-712
- Koushik Maharatna, Alfonso Troya, Milos Krstic, Eckhard Grass, Ulrich Jagdhold: A CORDIC like processor for computation of arctangent and absolute magnitude of a vector. 713-716
- Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner: Dynamic power optimization of the trace-back process for the Viterbi algorithm. 721-724
- Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re: Low-power implementation of polyphase filters in Quadratic Residue Number system. 725-728
- Quoc-Hoang Duong, Trung-Kien Nguyen, Sang-Gug Lee: Ultra low-voltage low-power exponential voltage-mode circuit with tunable output range. 729-732
- Sangjin Hong, Shu-Shin Chin, Magesh Sadasivam: Glitching power reduction through supply voltage adaptation mechanism for low power array structure design. 733-736
- Suh Ho Lee, Seon Wook Kim, Suki Kim: Implementation of a low power motion detection camera processor using a CMOS Image Sensor. 737-740
- Hwang-Cherng Chow, Shu-Hsien Chang: High performance sense amplifier circuit for low power SRAM applications. 741-744
- Mindaugas Drazdziulis, Per Larsson-Edefors: Evaluation of power cut-off techniques in the presence of gate leakage. 745-748
- Sabino Salerno, Enrico Macii, Massimo Poncino: Crosstalk energy reduction by temporal shielding. 749-752
- Cheong Kun, Shaolei Quan, Andrew Mason: A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead. 753-756
- Tsung-Han Tsai, Shih-Way Huang, Yi-Wen Wang: Architecture design of MDCT-based psychoacoustic model co-processor in MPEG advanced audio coding. 761-764
- Minyi Fu, Graham A. Jullien, Vassil S. Dimitrov, Majid Ahmadi: A low-power DCT IP core based on 2D algebraic integer encoding. 765-768
- Rei-Chin Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen: A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. 769-772
- Kai Huang, Fan-Min Li, Pei-Ling Shen, An-Yeu Wu: VLSI design of dual-mode Viterbi/turbo decoder for 3GPP. 773-776
- Kun-Bin Lee, Hui-Cheng Hsu, Chein-Wei Jen: A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization. 777-780
- Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang: A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. 781-784
- Venkat Srinivasan, Dong Sam Ha, Jos Sulistyo: Gigahertz-range MCML multiplier architectures. 785-788
- Wenjing Zhang, Graham A. Jullien, Vassil S. Dimitrov: A programmable base 2D-LNS MAC with self-generated look-up tables. 789-792
- Masahiro Sakamoto, Shuusaku Mizukami, Daisuke Hamano, Hisato Fujisaka: A design of 4-operand redundant binary parallel adder using neuron MOS. 793-796
- Michael Chappell, Alistair McEwan: A low power high speed accumulator for DDFS applications. 797-800
- Artur Wróblewski, Marek Wróblewski, Christoph Saas, Josef A. Nossek: Reduced binary tree FIR Filters. 801-804
- Prasanna Balasundaram, Karthik Vaidyanathan, Andrew Mason: Microsystem controller for sensor network control and data correction. 809-812
- Jameel Ahmed, Chaitali Chakrabarti: A dynamic task scheduling algorithm for battery powered DVS systems. 813-816
- Adrian Burian, Jarmo Takala: VLSI-efficient implementation of full adder-based median filter. 817-820
- Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen: Static floating-point unit with implicit exponent tracking for embedded DSP. 821-824
- Ashis Kumar Mal, Arindam Basu, Anindya Sundar Dhar: Sampled analog architecture for DCT and DST. 825-828
- Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen: B-spline factorization-based architecture for inverse discrete wavelet transform. 829-832
- Chung-Ping Hung, Sau-Gee Chen, Kun-Lung Chen: Design of an efficient variable-length FFT processor. 833-836
- Jin-Hua Hong, Bin-Yan Tsai, Liang-Te Lu, Shao-Hui Shieh: A novel radix-4 bit-level modular multiplier for fast RSA cryptosystem. 837-840
- Bin Cao, Thambipillai Srikanthan, Chip-Hong Chang: Design of residue-to-binary converter for a new 5-moduli superset residue number system. 841-844
- Apostolos P. Fournaris, Odysseas G. Koufopavlou: GF(2/sup K/) multipliers based on Montgomery Multiplication Algorithm. 849-852
- Takashi Hisakado, Hiroyoshi Iketo, Kohshi Okumura: Logically reversible arithmetic circuit using pass-transistor. 853-856
- Henning Gundersen, Yngvar Berg: Max and min functions using Multiple-Valued Recharged Semi-Floating Gate circuits. 857-860
- Luis Fortino Cisneros Sinencio, Alejandro Díaz-Sánchez, Jaime Ramírez-Angulo: A novel serial multiplier using floating-gate transistors. 861-864
- Quoc-Hoang Duong, Trung-Kien Nguyen, Sang-Gug Lee: CMOS exponential current-to-voltage circuit based on newly proposed approximation method. 865-868
- Vasanth Kakani, Foster F. Dai, Richard C. Jaeger: Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits. 869-872
- Young-Jun Lee, Yong-Bin Kim: A fast and precise interconnect capacitive coupling noise model. 873-876
- Yongquan Fan, Zeljko Zilic: A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. 877-880
- Kwang-Il Oh, Lee-Sup Kim: A high performance low power dynamic PLA with conditional evaluation scheme. 881-884
- Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux: An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. 885-888
- Chiu-Wah Ng, Tung-Sang Ng, Kun-Wah Yip: A unified architecture of MD5 and RIPEMD-160 hash algorithms. 889-892
- Paris Kitsos, Odysseas G. Koufopavlou: Whirlpool hash function: architecture and VLSI implementation. 893-896
- Alejandro Martínez-Ramírez, Alejandro Díaz-Sánchez, Mónico Linares Aranda, Javier Vega-Pineda: An architecture for fractal image compression using quad-tree multiresolution. 897-900
- Wai-Chi Fang, Michael Y. Jin: On board processor development for NASA's spaceborne imaging radar with VLSI system-on-chip technology. 901-904
- Dan Crisu, Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha: Low cost and latency embedded 3D graphics reciprocation. 905-908
- Mircea R. Stan: Systolic counters with unique zero state. 909-912
- Natalia Kazakova, Martin Margala, Nelson G. Durdle: Sobel edge detection processor for a real-time volume rendering system. 913-916
- Volkan Kursun, Eby G. Friedman: Forward body biased keeper for enhanced noise immunity in domino logic circuits. 917-920
- Christine Kwong, Bhaskar Chatterjee, Manoj Sachdev: Modeling and designing energy-delay optimized wide domino circuits. 921-924
- Kavitha Seshadri, Adrianne Pontarelli, Gauri Joglekar, Gerald E. Sobelman: Design techniques for Pulsed Static CMOS. 929-932
- Chua-Chin Wang, Ya-Hsin Hsueh, Sen-Fu Hong, Rong-Sui Kao: A phase-adjustable negative phase shifter using a single-shot locking method. 933-936
- Lien-Fei Chen, Yeong-Kang Lai: VLSI architecture of the reconfigurable computing engine for digital signal processing applications. 937-940
- Mary Kiemb, Kiyoung Choi: Application-specific configuration of multithreaded processor architecture for embedded applications. 941-944
- Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang: RLC effects on worst-case switching pattern for on-chip buses. 945-948
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-06-18T214307 by the dblp team