Maysam Ghovanloo, Khalil Najafi: A high-rate frequency shift keying demodulator chip for wireless biomedical implants.
45-48
Andrea Gerosa, Andrea Neviani: A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V.
49-52
Reza Sedaghat: A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation.
213-216
S. Wei, K. Shimizu: Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic.
221-224
Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin: A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining.
293-296
Hojun Kim, Jin-Gyun Chung: Minimizing switching activity in input word by offset and its low power applications for FIR filters.
297-300
Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki: Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming.
309-312
Mohammad M. Mansour, Amit Mehrotra: Efficient core designs based on parameterized macrocells with accurate delay models.
517-520
Chien-In Henry Chen, Kiran George: Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].
521-524
Meigen Shen, Li-Rong Zheng, Hannu Tenhunen: Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip.
585-588
Byoung-Woon Kim, Chong-Min Kyung: System-on-Chip design using intellectual properties with imprecise design costs.
625-628
Nattawut Thepayasuwan, Hua Tang, Alex Doboli: An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications.
629-632
Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong: A systolic multiplier with LSB first algorithm over GF(2/sup m/) which is as efficient as the one with MSB first algorithm.
633-636
Yonghee Im, Kaushik Roy: A logic-aware layout methodology to enhance the noise immunity of domino circuits.
637-640
Amine Bermak: A highly scalable 3D chip for binary neural network classification applications.
685-688
Radu Dogaru, Ioana Dogaru, Manfred Glesner: Compact image compression using simplicial and ART neural systems with mixed signal implementations.
689-692
Neyir Ozcan, Sabri Arik, Vedat Tavsanoglu: New criteria for the existence of stable equilibrium points in nonsymmetric cellular neural networks.
753-756
Jonne Poikonen, Ari Paasio: An area-efficient full-wave current rectifier for analog array processing.
757-760
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