Bangkok, Thailand - Volume 5
, Martin Jenkner
, Meinrad Schienle
, Christian Paulus
, Birgit Holzapfl
, Petra Schindler-Bauer
, Franz Hofmann
, D. Kuhlmeier
, J. Krause
, J. Albers
, W. Gumbrecht
, Doris Schmitt-Landsiedel
, Roland Thewes
: Design of an integrated potentiostat circuit for CMOS bio sensor chips.
, Andrea Neviani
: A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V.
, Chia-Sheng Tsai
: Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit.
K.-C. B. Tan
, T. Arslan
: Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture.
: A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation.
, K. Shimizu
: Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic.
: Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers.
, Jin-Gyun Chung
: Minimizing switching activity in input word by offset and its low power applications for FIR filters.
, Chi-Ying Tsui
, Wing-Hung Ki
: Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming.
, Tughrul Arslan
: A triple port RAM based low power commutator architecture for a pipelined FFT processor.
Jader A. De Lima
: An active leakage-injection scheme applied to low-voltage SRAMs.
Sei Hyung Jang
: A new synchronous mirror delay with an auto-skew-generation circuit.
P. C. Chen
, James B. Kuo
: Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI.
Chien-In Henry Chen
, Kiran George
: Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST].
Klaus D. Maier
: On-chip debug support for embedded Systems-on-Chip.
: Reducing the number of variable movements in exact BDD minimization.
, Kaushik Roy
: A logic-aware layout methodology to enhance the noise immunity of domino circuits.
, Alan F. Murray
: Mixed-signal VLSI implementation of the Products of Experts' contrastive divergence learning scheme.
, Kazuhiko Nakazawa
: Analog continuous-time recurrent decision circuit with high signal-voltage symmetry and delay-time equality.
Mohammed A. Hasan
: Algorithms for computating principal and minor invariant subspaces of large matrices.
: A highly scalable 3D chip for binary neural network classification applications.
, Lei Xu
: Medical data mining model for oriental medicine via BYY Binary Independent Factor Analysis.
: Global asymptotic stability of a larger class of delayed neural networks.
, Zhiping Lin
: Global optimization of neural network weights using subenergy tunneling function and ripple search.
Radu P. Matei
: Cellular neural networks with second-order cells and their pattern forming properties.
: Pulse mode neuron with leakage integrator and additive random noise.
: A wide-field direction-selective aVLSI spiking neuron.