International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia.
IEEE 2001, ISBN 0-7803-6685-9
Sydney, Australia - Volume 4
: Nonuniform amplitude division for ABLMS equalisation.
, Yu-Chuan Shu
: VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation.
F. S. Tsai
, Chen-Yi Lee
: A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system.
K. Y. Cheung
: CRRDL: a novel charge recovery-recycling differential logic.
: Leakage power estimation and minimization in VLSI circuits.
, Jouni Isoaho
: Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units.
: A novel ACS-feedback scheme for generic, sequential Viterbi-decoder macros.
: A low power survivor memory unit for sequential Viterbi-Decoders.
, Jack Wills
, John Choma Jr.
: On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters.
, An-Yeu Wu
: An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter.
Scott D. Huss
, John Bennett
: An efficient model for twisted-pair cables with discontinuities and stubs for discrete time simulations.
B. Siddik Yarman
, Ahmet Aksen
: A reflectance-based computer aided modelling tool for high speed/high frequency communication systems.
: Cellular-array power-sum circuits over programmable finite field GF(2''').
, Mohammed Ismail
: A single-chip CMOS front-end receiver architecture for multi-standard wireless applications.
Hung Yan Cheung
, King Sau Cheung
, J. Lau
: A low power monolithic AGC with automatic DC offset cancellation for direct conversion hybrid CDMA transceiver used in telemetering.
, Kwyro Lee
: Reconfigurable and programmable minimum distance search engine for portable video compression systems.
V. K. Jain
: Hybrid wavelet/spread-spectrum system for broadband wireless LANs.
, Keshab K. Parhi
: Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec.
: Control loop for optimization of power consumption in VLSI designs.
, M. Green
: New structures for very high-frequency CMOS clock dividers.
: A low cost 2-D inverse discrete cosine transform design for image compression.
: A new DA-based array for one dimensional discrete Hartley transform.
, R. Pieper
: A VLSI implementation of a universal programmable low sensitivity sampled data filter.
, Kai He
: A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications.
: A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor.
, Tung-Yang Chen
: Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes.
K. T. Christensen
: Design and optimization of CMOS switches for switched tuning of LC resonators.
, Mourad N. El-Gamal
: A 2.3 V low noise, low power, 10 GHz bandwidth Si-bipolar transimpedance preamplifier for optical receiver front-ends.
, Yichuang Sun
: Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm.
: Emerging adaptive antenna techniques for wireless ad-hoc networks.
, Y. Bajot
, H. Mehrez
: A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic.