ISCAS 1999:
Orlando, Florida, USA - Volume 6
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Axel Wenzler ,
Ernst Lücker :
Analysis of the periodic steady-state in nonlinear circuits using an adaptive function base.
1-4
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conf/iscas/CarastroPMBJ99 export record as
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conf/iscas/KouwenhovenMSR99 export record as
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conf/iscas/EfthivoulidisT99 export record as
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conf/iscas/KuijstermansDSKSR99 export record as
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M. Keramat :
Theoretical bases of convolution technique in gradient estimation of average quality index of electronic circuits.
73-76
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conf/iscas/Martinez-CastilloS99 export record as
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P. A. Ramamoorthy :
Nonlinear signal processor design: a building block approach.
101-104
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R. J. Pieper ,
S. Michael :
Circuit modeling to predict the performance of force-cooled cold plate structures.
105-108
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D. L. Youngblood :
Multi-mode impedance synthesis for subscriber line applications.
113-116
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Guo-Hui Lin ,
Guoliang Xue :
Balancing Steiner minimum trees and shortest-path trees in the rectilinear plane.
117-120
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K. Tsuji :
Structural properties for transformation of extended marked graphs.
129-132
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conf/iscas/ThulasiramanDHA99 export record as
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conf/iscas/SarrafzadehT99 export record as
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John P. Fishburn :
Optimization-based calibration of a static timing analyzer to path delay measurements.
186-189
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Jinghong Chen ,
Sung-Mo Kang :
A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits.
194-197
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E. Gondro ,
P. Klein ,
F. Schuler :
An analytical source-and-drain series resistance model of quarter micron MOSFETs and its influence on circuit simulation.
206-209
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J. H. Wang :
Event-overlapping processing in current waveform simulation.
226-229
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conf/iscas/MyonoNKISSIK99 export record as
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conf/iscas/ChatzigeorgiouNTK99 export record as
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R. Lowther :
Compact modeling of interconnect and substrate coupling at GHz frequencies.
238-241
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Haksu Kim ,
Dian Zhou :
An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles.
258-261
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D. Stroobannt :
PIN count prediction in ratio cut partitioning for VLSI and ULSI.
262-265
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T. Watanabe ,
H. Asai :
Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method.
266-269
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Robert H. Caverly ,
N. Quinn :
A SPICE model for simulating the impedance-frequency characteristics of high frequency PIN switching diodes.
282-285
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Zbigniew Galias :
Proving the existence of periodic solutions using global interval Newton method.
294-297
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F. Bonani ,
Marco Gilli :
A harmonic balance approach to bifurcation analysis of limit cycles.
298-301
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L. A. MacEachern :
Constrained circuit optimization via library table genetic algorithms.
310-313
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V. Borich ,
J. East ,
G. Haddad :
A fixed-point harmonic balance approach for circuit simulation under modulated carrier excitation.
346-349
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conf/iscas/NagavarapuYLG99 export record as
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Z. X. Shen ,
C. C. Jong :
A lower bound on general minimal resource interval scheduling with arbitrary component selection.
378-381
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conf/iscas/KrolikoskiSSRM99 export record as
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P. P. Jain :
Cost-effective co-verification using RTL-accurate C models.
460-463
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G. J. Bunza :
Towards systems integration in a virtual environment: small steps, big results, and complications to come for embedded systems engineering in the next millennium.
464-467
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J. Kenney :
Co-verification as risk management: minimizing the risk of incorporating a new processor in your next embedded system design.
474-477
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Jong-Nam Kim ,
Tae-Sun Choi :
Fast motion estimation using UESA, threshold-half-stop and adaptive partial sum scan from gradient magnitude.
497-500
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Wen-Cheng Yen ,
Chung-Yu Wu :
A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level.
505-508
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