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Semantic Scholar14. ISCA 1987: Pittsburgh, PA, USA
Daniel C. St. Clair:
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, PA, USA, June 1987. 1987, ISBN 0-8186-0776-9- David R. Ditzel, Hubert R. McLellan:
Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero. 2-9 - Gurindar S. Sohi, Sriram Vajapeyam:
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. 27-34 - Kenneth F. Wong, Mark A. Franklin:
Performance Analysis and Design of a Logic Simulation Machine. 46-55 - Satoshi Fujita, Reiji Aibara, Masafumi Yamashita, Tadashi Ae:
A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture. 64-70 - Bilha Mendelson, Gabriel M. Silberman:
Mapping Data Flow Programs on a VLSI Array of Processors. 72-80 - Dipak Ghosal, Laxmi N. Bhuyan:
Analytical Modeling and Architectural Modifications of a Dataflow Computer. 81-89 - Masaru Takesue:
A Unified Resource Management and Execution Control Mechanism for Data Flow Machines. 90-97 - Shigeo Abe, Tadaaki Bandoh, S. Yamaguchi, Ken-ichi Kurosawa, Kaori Kiriyama:
High Performance Integrated Prolog Processor IPP. 100-107 - Pierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni:
An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. 117-126 - Olivier Ridoux:
Deterministic and Stochastic Modeling of Parallel Garbage Collection - Towards Real-Time Criteria. 128-136 - Chengzheng Sun, Tzu Yungui:
The Sharing of Environment in AND-OR-Parallel Execution of Logic Programs. 137-144 - Aloke Guha, Raja Ramnarayan, Matthew Derstine:
Architectural Issues in Designing Symbolic Processors in Optics. 145-151 - Anujan Varma, Cauligi S. Raghavendra:
Rearrangeability of Multistage Shuffle/Exchange Networks. 154-162 - Ramón Beivide, Enrique Herrada, José L. Balcázar, Jesús Labarta:
Optimized Mesh-Connected Networks for SIMD and MIMD Architectures. 163-170 - David T. Harper III, J. Robert Jump:
Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks. 171-175 - Umakishore Ramachandran, Marvin H. Solomon, Mary K. Vernon:
Hardware Support for Interprocess Communication. 178-188 - William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills:
Architecture of a Message-Driven Processor. 189-196 - Manoj Kumar:
Effect of Storage Allocation/Reclamation Methods on Parallelism and Storage Requirements. 197-205 - Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. 224-231 - Christoph Scheurich, Michel Dubois:
Correct Memory Operation of Cache-Based Multiprocessors. 234-243 - Andrew W. Wilson Jr.:
Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors. 244-252 - Timothy J. Stanley, Robert G. Wedig:
A Performance Analysis of Automatically Managed Top of Stack Buffers. 272-281 - Brian B. Moore, Andris Padegs, Ronald M. Smith, Werner Buchholz:
Concepts of the System/370 Vector Architecture. 282-288 - Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter:
WISQ: A Restartable Architecture Using Queues. 290-299 - David R. Ditzel, Hubert R. McLellan, Alan D. Berenbaum:
The Hardware Architecture of the CRISP Microprocessor. 309-319
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