Google
Google Scholar
MS Academic
CiteSeerX
CORE
Semantic Scholar7. ISCA 1980
Jacques Lenfant, Barry R. Borgerson, Daniel E. Atkins, Keki B. Irani, David Kinniment, Hideo Aiso:
Proceedings of the 7th Annual Symposium on Computer Architecture, May 1980. ACM 1980- Jack B. Dennis, G. Andrew Boughton, Clement K. C. Leung:
Building Blocks for Data Flow Prototypes. 1-8 - F. André, Jean-Pierre Banâtre, Hughes Leroy, G. Paget, Florimond Ployette, Jean-Paul Routeau:
Kensur: An Architecture Oriented Towards Programming Languages Translation. 17-22 - Karl-Erwin Großpietsch, Jörg Kaiser, Edgar Nett:
A Concept for Test and Reconfiguration of a Fault-Tolerant VLSI Processor System. 37-43 - Robert J. McMillen, Howard Jay Siegel:
MIMD Machine Communication Using the Augmented Data Manipulator Network. 51-60 - Edward G. Coffman Jr., Kimming So:
On the Comparison Between Single and Multiple Processor Systems. 72-79 - V. Carl Hamacher, Gerald S. Shedler:
Performance of a Collision-Free Local Bus Network Having Asynchronous Distributed Control. 80-87 - David R. Ditzel, David A. Patterson:
Retrospective on High-Level Language Computer Architecture. 97-104 - Philip C. Trevleaven, Geoffrey F. Mole:
A Multi-Processor Reduction Machine for User-Defined Reduction Languages. 121-130 - Jeffrey M. Tobias:
A Single User Multiprocessor Incorporating Processor Manipulation Facilities. 131-138 - Robert H. Halstead Jr., Stephen A. Ward:
The Munet: A Scalable Decentralized Architecture For Parallel Computers. 139-145 - David B. G. Edwards, Alan E. Knowles, J. V. Woods:
MU6-G: A New Design to Achieve Mainframe Performance from a Mini-Sized Computer. 161-167 - Hermann von Issendorff, W. Grunewald:
An Adaptable Network for Functional Distributed Systems. 196-201 - Mokhtar Boshra Riad:
A Combination of Field and Current Access Techniques for Effiecient and Cost-Effective Bubble Memories. 202-210 - Kishor S. Trivedi:
Designing Linear Storage Hierarchies so as to Maximize Reliability Subject to Cost and Performance Constraints. 211-217 - Sudhir Ahuja, Charles S. Roberts:
An Associative/Parallel Processor for Partial Match Retrieval Using Superimposed Codes. 218-227 - Miguel Garcia Hoffman:
Hardware Implementation of Communication Protocols: A Formal Approach. 253-263 - P. Guillier, D. Slosberg:
An Architecture with Comprehensive Facilities of Inter-Process Synchronization and Communication. 264-270 - Robert M. Lougheed, David L. McCubbrey:
The Cytocomputer: A Practical Pipelined Image Processor. 271-277 - Constantine Halatsis, Andries van Dam, J. Joosten, M. Letheren:
Architectural Considerations for a Microprogrammable Emulating Engine Using Bitslices. 278-291 - Uwe Hercksen, Rainer Klar, Wolfgang Kleinöder:
Hardware-Measurements of Storage Access Conflicts in the Processor Array EGPA. 317-324 - Mario Tokoro, Kiichiro Tamaru, Masaaki Mizuno, Masao Hori:
A High-Level Multi-Lingual Multiprocessor KMP. 325-333
maintained by 
at 
at 
data released under the ODC-BY 1.0 license; see also our legal information page
last updated on 2017-10-20 01:46 CEST by the dblp team