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ORCID4th ISCA 1977
- Harold S. Stone, Bruce Wald, Y. S. Wu:
Proceedings of the 4th Annual Symposium on Computer Architecture, College Park, MD, USA, March 1977. ACM 1977, ISBN 978-1-4503-7911-3 - Yaohan Chu:
Architecture of a Hardware Data Interpreter. 1-9 - Subrata Dasgupta, Simon Fraser:
The Design of Some Language Constructs for Horizontal Microprogramming. 10-16 - E. Douglas Jensen, Richard Y. Kain:
The Honeywell Modular Microprogram Machine: M3. 17-28 - Richard R. Ramseyer, Andries van Dam:
A Multi-Microprocessor Implementation of a General Purpose Pipelined CPU. 29-34 - C. V. Ravi, Torben Moller:
A Hierarchical Microcomputer System for Hardware and Software Development. 35-40 - J. Archer Harris, David R. Smith:
Hierarchical Multiprocessor Organizations. 41-48 - Ken Murakami, Seishi Nishikawa, M. Soto:
Poly-Processor System Analysis and Design. 49-56 - Guy Mazaré:
A Few Examples of How to Use a Symmetrical Multi-Micro-Processor. 57-62 - Peter M. Kogge:
The Microprogramming of Pipelined Processors. 63-70 - Howard Jay Siegel:
The Universality of Various Types of SIMD Machine Interconnection Networks. 70-79 - B. Ramakrishna Rau, George E. Rossman:
The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. 80-89 - S. R. Ahuja, J. Robert Jump:
A Modular Memory Scheme for Array Processing. 90-94 - Leonard S. Haynes:
The Architecture of an ALGOL 60 Computer Implemented with Distributed Processors. 95-104 - Herbert Sullivan, Theodore R. Bashkow:
A Large Scale, Homogeneous, Fully Distributed Parallel Machine, I. 105-117 - Herbert Sullivan, Theodore R. Bashkow, David Klappholz:
A Large Scale, Homogeneous, Fully Distributed Parallel Machine, II. 118-124 - G. Jack Lipovski:
On Virtual Memories and Micronetworks. 125-134 - Jon C. Strauss, Kenneth J. Thurber:
Considerations for New Tactical Computer Systems. 135-140 - Kenneth J. Thurber, Peter C. Patton, Robert C. Deward, Jon C. Strauss, Thomas W. Petschauer:
An Advanced Tactical Computer Concept. 141-146 - Gary J. Nutt:
Microprocessor Implementation of a Parallel Processor. 147-152 - Paul E. Dworak, Alice C. Parker, Richard Blum:
The Design and Implementation of a Real-Time Sound Generation System. 153-158 - Alice C. Parker, Andrew W. Nagle:
Hardware/Software Tradeoffs in A Variable Word Width, Variable Queue Length Buffer Memory. 159-164 - Bernard L. Peuto, Leonard J. Shustek:
An Instruction Timing Model of CPU Performance. 165-178 - Cornelis H. Hoogendoorn:
Reduction of Memory Interference in Multiprocessor Systems. 179-183 - Dan W. Hammerstrom, Edward S. Davidson:
Information Content of CPU Memory Referencing Behavior. 184-192 - Ming T. Liu, Cecil C. Reames:
Message Communication Protocol and Operation System Design for the Distributed Loop Computer Network (DLCN). 193-200 - G. H. Poujoulat:
Architecture of the Corail Building Block System. 201-204 - H. L. Tredennick, Terry A. Welch:
High-Speed Buffering for Variable Length Operands. 205-210
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