38. ISCA 2011:
San Jose,
CA,
USA
Ravi Iyer, Qing Yang, Antonio González (Eds.):
38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA.
ACM 2011, ISBN 978-1-4503-0472-6
Novel architectures
- Atif Hashmi, Hugues Berry, Olivier Temam, Mikko H. Lipasti:
Automatic abstraction and fault tolerance in cortical microachitectures.
1-10
- Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg:
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template.
11-22
- Erika Gunadi, Mikko H. Lipasti:
CRIB: consolidated rename, issue, and bypass.
23-32
Parallel architectures I
Caches
- Daniel Sanchez, Christos Kozyrakis:
Vantage: scalable and efficient fine-grain cache partitioning.
57-68
- Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das:
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.
69-80
- Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramoney:
Bypass and insertion algorithms for exclusive last-level caches.
81-92
- Blas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato:
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks.
93-104
Parallel architectures II
- Jungju Oh, Milos Prvulovic, Alenka G. Zajic:
TLSync: support for multiple fast barriers using on-chip transmission lines.
105-116
- Neal Clayton Crago, Sanjay J. Patel:
OUTRIDER: efficient memory latency tolerance with decoupled strands.
117-128
- Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators.
129-140
- Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt:
Prefetch-aware shared resource management for multi-core systems.
141-152
Dependable architectures
Security
- Siddhartha Chhabra, Yan Solihin:
i-NVMM: a secure non-volatile main memory system with incremental encryption.
177-188
- Mohit Tiwari, Jason Oberg, Xun Li, Jonathan Valamehr, Timothy E. Levin, Ben Hardekopf, Ryan Kastner, Frederic T. Chong, Timothy Sherwood:
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security.
189-200
Reliability
Multithreading
- Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron:
Energy-efficient mechanisms for managing thread context in throughput processors.
235-246
- Wing-Kei S. Yu, Ruirui C. Huang, Sarah Q. Xu, Sung-En Wang, Edwin Kan, G. Edward Suh:
SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading.
247-258
On-chip networks I
Memory
Power I
- David Meisner, Christopher M. Sadler, Luiz André Barroso, Wolf-Dietrich Weber, Thomas F. Wenisch:
Power management of online data-intensive services.
319-330
- Susmit Biswas, Mohit Tiwari, Timothy Sherwood, Luke Theogarajan, Frederic T. Chong:
Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management.
331-340
- Sriram Govindan, Anand Sivasubramaniam, Bhuvan Urgaonkar:
Benefits and limitations of tapping into stored energy for datacenters.
341-352
Architecture modeling and evaluation
- John Demme, Simha Sethumadhavan:
Rapid identification of architectural bottlenecks via precise event counting.
353-364
- Hadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, Doug Burger:
Dark silicon and the end of multicore scaling.
365-376
- Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen:
Moguls: a model to explore the memory hierarchy for bandwidth improvements.
377-388
On-chip networks II
Photonics
- Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.
425-436
- Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn:
The role of optics in future high radix switch design.
437-448
- Kai Ma, Xue Li, Ming Chen, Xiaorui Wang:
Scalable power control for many-core architectures running multi-threaded applications.
449-460
- Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu:
Energy-efficient cache design using variable-strength error-correcting codes.
461-472
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