33. ISCA 2006: Boston, MA, Wisconsin, USA

Introduction

• Message from the General Chair.
  
• Message from the Program Chair.
  
• Reviewers.
  
• SIGARCH Guidelines.
  

Keynote 1

• Yale N. Patt:
  Computer Architecture Research and Future Microprocessors: Where Do We Go from Here? 2
  

Session 1: Interconnection Networks

• Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park:
  A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks. 4-15
  
• Steve Scott, Dennis Abts, John Kim, William J. Dally:
  The BlackWidow High-Radix Clos Network. 16-28
  

Session 2: Memory Models

• Arvind, Jan-Willem Maessen:
  Memory Model = Instruction Reordering + Store Atomicity. 29-40
  
• Christoph von Praun, Harold W. Cain, Jong-Deok Choi, Kyung Dong Ryu:
  Conditional Memory Ordering. 41-52
  
• Austen McDonald, JaeWoong Chung, Brian D. Carlstrom, Chi Cao Minh, Hassan Chafi, Christos Kozyrakis, Kunle Olukotun:
  Architectural Semantics for Practical Transactional Memory. 53-65
  

Session 3: Power and Thermal Management

• Parthasarathy Ranganathan, Phil Leech, David E. Irwin, Jeffrey S. Chase:
  Ensemble-level Power Management for Dense Blade Servers. 66-77
  
• James Donald, Margaret Martonosi:
  Techniques for Multicore Thermal Management: Classification and New Exploration. 78-88
  
• Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Krisztián Flautner:
  SODA: A Low-power Architecture For Software Radio. 89-101
  

Session 4: Multicore

• Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmoy Ghosh:
  An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors. 102-113
  
• Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang, John Paul Shen:
  Multiple Instruction Stream Processor. 114-127
  

Keynote 2

• Philip G. Emma:
  The End of Scaling? Revolutions in Technology and Microarchitecture as We Pass the 90 Nanometer Node. 128
  

Session 5A: Memory Access Issues

• Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir:
  Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. 130-141
  
• Alok Garg, M. Wasiur Rashid, Michael C. Huang:
  Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification. 142-154
  

Session 5B: Cache Design I

• Chuanjun Zhang:
  Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches. 155-166
  
• Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt:
  A Case for MLP-Aware Cache Replacement. 167-178
  

Session 6A: Security and Network Processors

• Chenyu Yan, Daniel Englender, Milos Prvulovic, Brian Rogers, Yan Solihin:
  Improving Cost, Performance, and Security of Memory Encryption and Authentication. 179-190
  
• Benjamin C. Brodie, David E. Taylor, Ron K. Cytron:
  A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching. 191-202
  
• Jahangir Hasan, Srihari Cadambi, Venkata Jakkula, Srimat T. Chakradhar:
  Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture. 203-215
  

Session 6B: Multithreading

• Christopher B. Colohan, Anastassia Ailamaki, J. Gregory Steffan, Todd C. Mowry:
  Tolerating Dependences Between Large Speculative Threads Via Sub-Threads. 216-226
  
• Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval:
  Bulk Disambiguation of Speculative Threads in Multiprocessors. 227-238
  
• Seungryul Choi, Donald Yeung:
  Learning-Based SMT Processor Resource Distribution via Hill-Climbing. 239-251
  

Session 7A: Cache Design II

• Stephen Somogyi, Thomas F. Wenisch, Anastassia Ailamaki, Babak Falsafi, Andreas Moshovos:
  Spatial Memory Streaming. 252-263
  
• Jichuan Chang, Gurindar S. Sohi:
  Cooperative Caching for Chip Multiprocessors. 264-276
  

Session 7B: Potpourri

• Shiliang Hu, James E. Smith:
  Reducing Startup Time in Co-Designed Virtual Machines. 277-288
  
• Qing Yang, Weijun Xiao, Jin Ren:
  TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time. 289-301
  

Session 8A: Dataflow

• Saisanthosh Balakrishnan, Gurindar S. Sohi:
  Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs. 302-313
  
• Steven Swanson, Andrew Putnam, Martha Mercaldi, Ken Michelson, Andrew Petersen, Andrew Schwerin, Mark Oskin, Susan J. Eggers:
  Area-Performance Trade-offs in Tiled Dataflow Architectures. 314-326
  

Session 8B: Cache Coherence

• Karin Strauss, Xiaowei Shen, Josep Torrellas:
  Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. 327-338
  
• Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter:
  Interconnect-Aware Coherence Protocols for Chip Multiprocessors. 339-351
  

Keynote 3

• Steve Herrod:
  The Future of Virtualization Technology. 352
  

Session 9: Quantum Computing

• Rodney Van Meter, Kae Nemoto, W. J. Munro, Kohei M. Itoh:
  Distributed Arithmetic on a Quantum Multicomputer. 354-365
  
• Nemanja Isailovic, Yatish Patel, Mark Whitney, John Kubiatowicz:
  Interconnection Networks for Scalable Quantum Computers. 366-377
  
• Darshan D. Thaker, Tzvetan S. Metodi, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong:
  Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing. 378-390
  

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