31. ISCA 2004: Munich, Germany

Architecture Evaluations

• Michael Bedford Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman P. Amarasinghe, Anant Agarwal:
  Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. 2-13
  
• Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das:
  Evaluating the Imagine Stream Architecture. 14-25
  
• John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu:
  Field-testing IMPACT EPIC research results in Itanium 2. 26-39
  

Parallelism in Microarchitectures

• T. N. Vijaykumar, Zeshan Chishti:
  Wire Delay is Not a Problem for SMT (In the Near Future). 40-51
  
• Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic:
  The Vector-Thread Architecture. 52-63
  
• Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas:
  Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. 64-75
  
• Yuan Chou, Brian Fahs, Santosh G. Abraham:
  Microarchitecture Optimizations for Exploiting Memory-Level Parallelism. 76-89
  

Memory Consistency

• Harold W. Cain, Mikko H. Lipasti:
  Memory Ordering: A Value-Based Approach. 90-101
  
• Lance Hammond, Vicky Wong, Michael K. Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun:
  Transactional Memory Coherence and Consistency. 102-113
  
• Sudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-Yeu Joseph Lu, Sridhar Narayanan:
  TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model. 114-123
  
• Mainak Chaudhuri, Mark Heinrich:
  SMTp: An Architecture for Next-generation Scalable Multi-threading. 124-137
  

Power and Energy

• Christopher J. Hughes, Sarita V. Adve:
  A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. 138-149
  
• John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong:
  Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. 150-161
  
• Roni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, Avi Mendelson:
  Power Awareness through Selective Dynamically Optimized Traces. 162-175
  

Interconnect and I/O

• Lakshmi N. Bairavasundaram, Muthian Sivathanu, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau:
  X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs. 176-187
  
• Robert D. Mullins, Andrew West, Simon W. Moore:
  Low-Latency Virtual-Channel Routers for On-Chip Networks. 188-197
  
• Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide:
  Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism. 198-211
  

Compression and Debugging

• Alaa R. Alameldeen, David A. Wood:
  Adaptive Cache Compression for High-Performance Processors. 212-223
  
• Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas:
  iWatcher: Efficient Architectural Support for Software Debugging. 224-237
  

Superscalars

• Sami Yehia, Olivier Temam:
  From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation. 238-249
  
• Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero:
  Prophet/Critic Hybrid Branch Prediction. 250-263
  

Support for Reliability

• Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt:
  Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. 264-275
  
• Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
  The Case for Lifetime Reliability-Aware Microprocessors. 276-287
  
• Michael D. Powell, T. N. Vijaykumar:
  Exploiting Resonant Behavior to Reduce Inductive Noise. 288-301
  

Register File

• J. Adam Butts, Gurindar S. Sohi:
  Use-Based Register Caching with Decoupled Indexing. 302-313
  
• Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero:
  A Content Aware Integer Register File Organization. 314-324
  
• Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi:
  Physical Register Inlining. 325-337
  

Performance Methodologies

• Tejas Karkhanis, James E. Smith:
  A First-Order Superscalar Processor Model. 338-349
  
• Lieven Eeckhout, Robert H. Bell Jr., Bastiaan Stougie, Koen De Bosschere, Lizy Kurian John:
  Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies. 350-363
  

Microarchitectural Concepts

• Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob:
  Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. 364-375
  
• Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam:
  A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. 376-386
  

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