31. ISCA 2004:
Munich, Germany Architecture Evaluations
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conf/isca/TaylorLMWBGHJKPSSSFAA04 Michael Bedford Taylor ,
Walter Lee ,
Jason E. Miller ,
David Wentzlaff ,
Ian Bratt ,
Ben Greenwald ,
Henry Hoffmann ,
Paul Johnson ,
Jason Sungtae Kim ,
James Psota ,
Arvind Saraf ,
Nathan Shnidman ,
Volker Strumpen ,
Matthew Frank ,
Saman P. Amarasinghe ,
Anant Agarwal :
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams.
2-13
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Parallelism in Microarchitectures
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conf/isca/KrashinskyBHGPCA04 export record as
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Memory Consistency
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conf/isca/HammondWCCDHPWKO04 export record as
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Power and Energy
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conf/isca/OliverRSCCJFAC04 John Oliver ,
Ravishankar Rao ,
Paul Sultana ,
Jedidiah R. Crandall ,
Erik Czernikowski ,
Leslie W. Jones IV ,
Diana Franklin ,
Venkatesh Akella ,
Frederic T. Chong :
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.
150-161
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Interconnect and I/O
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conf/isca/BairavasundaramSAA04 export record as
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Compression and Debugging
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Superscalars
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Sami Yehia ,
Olivier Temam :
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation.
238-249
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Support for Reliability
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conf/isca/SrinivasanABR04 export record as
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Register File
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Performance Methodologies
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Microarchitectural Concepts
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