8. IOLTW 2002: Isle of Bendor, France
8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France. IEEE Computer Society 2002 ISBN 0-7695-1641-6
Hardware Fault Tolerance
- Daniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra: Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. 8-12
Hardware-Software Design and Validation of Fault Tolerant Systems
- Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka: Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods. 21-25
- Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto: Automated Synthesis of SEU Tolerant Architectures from OO Descriptions. 26-31
- Cristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto: A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems. 32-
Self Checking Circuits
- Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel: A New Self-Checking Code-Disjoint Carry-Skip Adder. 39-43
- Ilya Levin, Vladimir Sinelnikov, Mark G. Karpovsky, Sergey Ostanin: Sequential Circuits Applicable for Detecting Different Types of Faults. 44-
Concurrent Error Detection I
- Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley: A High Speed Encoder for Recursive Systematic Convolutive Codes. 51-55
- Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis: A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. 56-60
- Huy Nguyen, Abhijit Chatterjee: Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems. 61-
Concurrent Error Detection II
- Matthias Pflanz, K. Walther, Christian Galke, Heinrich Theodor Vierhaus: On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check. 69-73
- Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin: A Statistical Sampler for a New On-line Analog Test Method. 79-
Analog and Mixed Signal Testing and Reliability
- Joan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio García: A BICS for CMOS Opamps by Monitoring the Supply Current Peak. 94-98
- Rosa Rodríguez-Montañés, D. Muñoz, L. Balado, Joan Figueras: Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours. 99-103
Fault Injection Techniques and Results
- Régis Leveugle, K. Hadjiat: Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. 107-111
- Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Analysis of SEU Effects in a Pipelined Processor. 112-116
- Gian-Carlo Cardarilli, F. Kaddour, A. Leandri, Marco Ottavi, Salvatore Pontarelli, Raoul Velazco: Bit Flip Injection in Processor-Based Architectures: A Case Study. 117-
BIST Techniques I
- Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz: A Low Power Pseudo-Random BIST Technique. 140-
BIST Techniques II
- Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis: Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. 152-157
- Dimitri Kagaris: Built-in Generation of m -Sequences with Irreducible Characteristic Polynomials. 158-
Testing Issues
- Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira: Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing. 165-169
- Giuseppe Di Gregorio, Maria Grazia La Rosa, Biagio Russo: Checkers for RF Matching Networks on an Automatic Test Board. 170-
Posters
- Carlo Dallavalle: Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test. 177
- Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus: On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures. 178
- Jose Miguel Vieira dos Santos: Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells. 179
- Naotake Kamiura, Kazuharu Yamato, Teijiro Isokawa, Nobuyuki Matsui: Learning-Based On-Line Testing in Feedforward Neural Networks. 180
- Adam Kristof: On-Line Detection of Short Circuits in Digital Devices and Systems. 183
- Mohammad A. Naal, M. Rakotoar, Emmanuel Simeu, Chouki Aktouf: Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach. 184
- Petros Oikonomakos, Mark Zwolinski: Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment. 185
- Aleksandra Rankov, Gaynor E. Taylor, John Webster: Robust Data Compression for Analogue Test Outputs. 186
- Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.: A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems. 187
- Ari Virtanen: Radiation Effects Facility RADEF. 188
- Ilia Polian, Martin Keim, Nicolai Mallig, Bernd Becker: Sequential n -Detection Criteria: Keep It Simple. 189
- Chouki Aktouf, Benoît Pannetier, Pierre Lemaître-Auger, Smail Tedjini: On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing Technology. 191
- Bartomeu Alorda, André Ivanov, Jaume Segura: An Off-Chip Sensor Circuit for On-Line Transient Current Testing. 192
- Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero: Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. 193
- Fernanda Gusmão de Lima, Luigi Carro, Raoul Velazco, Ricardo Augusto da Luz Reis: Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller. 194
- F. Kaddour, Sana Rezgui, Raoul Velazco, S. Rodriguez, J. R. De Mingo: Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach. 195
Memory BIST Analysis and Application
- Alvin Jee: Defect-Oriented Analysis of Memory BIST Tests. 201-205
- Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda: A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. 206-210
Memory ECC and Soft Errors
- Daniele Rossi, Cecilia Metra, Bruno Riccò: Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. 221-225
- Bernard Coloma, Patrick Delaunay, Olivier Husson: High Speed 15 ns 4 Mbits SRAM for Space Application. 226-
High Reliability in Railway and Automotive Systems
- D. Bied-Charreton, D. Guillon, B. Jacques: The YATE Fail-Safe Interface: The User's Point of View. 233-
- Alberto Manzone, Diego De Costantini: Fault Tolerant Insertion and Verification: A Case Study. 238-242
- Luca Schiano, Cecilia Metra, Diego Marino: Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. 243-
Embedded Memory Yield Enhancement
- Emmanuel Rondey, Yann Tellier, Simone Borri: A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios. 251-255
- Valery A. Vardanian, Yervant Zorian: A March-Based Fault Location Algorithm for Static Random Access Memories. 256-261
- Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu: A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. 262-
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