13. IOLTS 2007:
Heraklion, Crete, Greece
Test Technology Educational Program (TTEP) 2007 Full-Day Tutorial
Keynote Talk
Mark Derbey:
Soft-Errors Phenomenon Impacts on Design for Reliability Technologies.
7
Invited Talk
Sanjiv Taneja:
Accelerating Yield Ramp through Real-Time Testing.
11
Session 1:
Reliability Issues in Nanometer Technologies
Session 2:
Network-on-Chip Reliability and Fault Tolerance
Session 3:
Secure Systems
Session 4:
Large Scale Dependability
Michel Pignol:
Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant Spacecraft Supercomputers.
85-92
Session 5:
Dependability of Processors, SoCs and Asynchronous Circuits
Special Session 1:
Aging and Wearout Issues and Mitigation Approaches
T. M. Mak:
Infant Mortality--The Lesser Known Reliability Issue.
122
Subhasish Mitra:
Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout.
123
Keynote Talk
Session 6:
Radiation Effects
Tino Heijmen:
Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs.
131-136
Claudia Rusu,
Antonin Bougerol,
Lorena Anghel,
Cécile Weulersse,
Nadine Buard,
S. Benhammadi,
Nicolas Renaud,
Guillaume Hubert,
Frederic Wrobel,
Thierry Carrière,
Rémi Gaillard:
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells.
137-145
Session 7:
Signal Integrity and Error Compensation
Special Session 2:
Panel:
SER Trends in 45nm and Beyond
Session 8:
Posters
Session 9:
Fault Tolerance
Session 10:
On-Line Testing for Analog, Mixed-Signal, RF and Delay Defect Tolerance
John Liobe,
Martin Margala:
Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test.
231-236
Special Session 3:
Fault-Tolerant and Self-Adapting Design to Mitigate Power, Yield and Reliability Issues in Upcoming Process Nodes
Asen Asenov:
Statistical Device Variability and its Impact on Yield and Performance.
253
Davide Pandini:
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies.
254
Michael Nicolaidis:
GRAAL: A Fault-Tolerant Architecture for Enabling Nanometric Technologies.
255
Special Session 4:
Reconfiguration and Fault Tolerance in Future Massively Parallel Multi-Core Chips
Session 11:
Processor-Based Testing
Steffen Tarnick:
Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters.
285-292
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