9. IOLTS 2003: Kos Island, Greece

9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece. IEEE Computer Society 2003, ISBN 0-7695-1968-7

@proceedings{DBLP:conf/iolts/2003,
  title     = {9th IEEE International On-Line Testing Symposium (IOLTS 2003),
               7-9 July 2003, Kos Island, Greece},
  booktitle = {IOLTS},
  publisher = {IEEE Computer Society},
  year      = {2003},
  isbn      = {0-7695-1968-7},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Keynote Talks

Ivo Bolsens:
Challenges and Opportunities for FPGA Programmable System Platforms. 3
Robert Baumann:
Technology Scaling Trends and Accelerated Testing for Soft Errors in Commercial Silicon Devices. 4-

On-Line Testing Approaches

Yi Zhao, Sujit Dey:
Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC. 7-11
Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis:
A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. 12-16
Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala:
On-Line Error Detecting Constant Delay Adder. 17-

Self Checking Circuits

Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld:
A Modulo p Checked Self-Checking Carry Select Adder. 25-29
Petros Oikonomakos, Mark Zwolinski:
Foundation of Combined Datapath and Controller Self-checking Design. 30-34
Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba:
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. 35-

Checker Designs

Steffen Tarnick:
A Design Method for Embedded Self-Testing t-UED and BUED Code Checkers. 43-48
A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. Nikitin:
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes. 49-53
Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
An Analog Checker With Input-Relative Tolerance for Duplicate Signals. 54-

Fault Tolerance

Daniele Rossi, Steven V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra:
Power Consumption of Fault Tolerant Codes: the Active Elements. 61-67
Joakim Aidemark, Peter Folkesson, Johan Karlsson:
On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time Redundancy. 68-74
André K. Nieuwland, Richard P. Kleihorst:
The positive effect on IC yield of embedded Fault Tolerance for SEUs. 75-

How Can Defect-Based Test Be Made to Work in a Foundry World?

Mohammad A. Naal, Emmanuel Simeu, Salvador Mir:
On-Line Testable Decimation Filter Design for AMS Systems. 83-88
D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
An Efficient BIST scheme for High-Speed Adders. 89-93
Michael Nicolaidis, Nadir Achouri, Lorena Anghel:
Memory Built-In Self-Repair for Nanotechnologies. 94-

Analysis and Modelling of Transient and Delay Faults

Matteo Sonza Reorda, Massimo Violante:
Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. 101-105
Chaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz:
An Improved Markov Source Design for Scan BIST. 106-110
Martin Omaña, Giacinto Papasso, Daniele Rossi, Cecilia Metra:
A Model for Transient Fault Propagation in Combinatorial Logic. 111-

Analysis and Verification of FPGA Faults

Massimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori:
Analyzing SEU Effects in SRAM-based FPGAs. 119-123
Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
Defect Analysis for Delay-Fault BIST in FPGAs. 124-128
Monica Alderighi, Sergio D'Angelo, Marcello Mancini, Giacomo R. Sechi:
A Fault Injection Tool for SRAM-based FPGAs. 129-

On-Line Testing of Microprocessor-Based Systems

Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray:
Low-Cost On-Line Fault Detection Using Control Flow Assertions. 137-143
Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
A Watchdog Processor to Detect Data and Control Flow Errors. 144-148
George Xenoulis, Dimitris Gizopoulos, Nektarios Kranitis, Antonis M. Paschalis:
Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores. 149-

Posters

Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris:
On Compaction-Based Concurrent Error Detection. 157
Victor Varshavsky, Ilya Levin, Vladimir Ostrovsky:
Increasing Implementability of beta-driven Threshold Checkers. 158
O. Goloubeva, Matteo Sonza Reorda, Massimo Violante:
An RT-level Concurrent Error Detection Technique for Data Dominated Systems. 159
Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, I. Solcia, Luca Tagliaferri:
FAUST: FAUlt-injection Script-based Tool. 160
S. R. Seward, Parag K. Lala:
Fault Injection in Digital Logic Circuits at the VHDL Level. 161
Monica Alderighi, Fabio Casini, Sergio D'Angelo, F. Faure, Marcello Mancini, Sandro Pastore, Giacomo R. Sechi, Raoul Velazco:
Radiation test methodology for SRAM-based FPGAs by using THESIC. 162
Fabian Vargas, Diogo B. Brum, Dárcio Prestes, Leticia Maria Veiras Bolzani, Eduardo Luis Rhod, Matteo Sonza Reorda:
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? 163
Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. 164-165
N. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu:
Analysis of Bit Transition Count for EDAC Encoded FSM. 166
Rodrigo Picos, Joan Font, Eugeni Isern, Miquel Roca, Eugenio García:
A Configurable Built in Current Sensor for Mixed Signal Circuit Testing. 167
Andrzej Krasniewski:
Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption. 168-

Merging On-Line and Off-Line Testing

Matthias Pflanz, Heinrich Theodor Vierhaus:
Control Signal Protection For High Performance Processors. 173-
Bartomeu Alorda, Jaume Segura:
An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. 178-182
Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus:
Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. 183-

When Will Soft Errors Become A Design Constraint?

Elmar Dilger, Matthias Gulbins, Thomas Ohnesorge, Bernd Straube:
On a Redundant Diversified Steering Angle. 191-196
Alberto Manzone, Claudio Genta:
Automatic toolset for fault tolerant design: results demonstration on a running industrial application. 197-201
D. J. Beauregard, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Savio N. Chau, Leon Alkalai:
Error-Injection-Based Failure Characterization of the IEEE 1394 Bus. 202-

Advanced Testing and Repair Issues

Raoul Velazco, Lorena Anghel, S. Saleh:
A Methodology for Test Replacement Solutions of Obsolete Processors. 209-213
L. Di Silvio, Daniele Rossi, Cecilia Metra:
Crosstalk Effect Minimization for Encoded Busses. 214-218
Dimitri Kagaris, Spyros Tragoudas:
InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs. 219-224

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