Synthesis and Modelling

• 
  Kees van Berkel: VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant Power. 1-11
• 
  Marly Roncken, Ronald Saeijs: Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy. 13-27
• 
  Ilana David, Ran Ginosar, Michael Yoeli: Self-Timed Architecture of a Reduced Instruction Set Computer. 29-43
• 
  O. Salomon, Heinrich Klar: Self-Timed Fully Pipelined Multipliers. 45-55

Theory and Specification

• 
  Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding: Normal Form in a Delay-Insensitive Algebra. 57-70
• 
  Alexandre Yakovlev, A. I. Petrov, Leonid Ya. Rosenblum: Synthesis of Asynchronous Control Circuits from Symbolic Signal Transition Graphs. 71-85
• 
  Meng-Lin Yu, P. A. Subrahmanyam: Hazard-Free Asynchronous Circuit Synthesis. 87-105
• 
  Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli: Automated Synthesis of Asynchronous Interface Circuits. 107-121
• 
  Mark B. Josephs, Jan Tijmen Udding: Implementing a Stack as a Delay-insensitive Circuit. 123-135
• 
  Jo C. Ebergen, P. F. Bertrand, S. Gingras: Solving a Mutual Exclusion Problem with the RGD Arbiter. 137-147

Engineering Practice

• 
  Jaco Haans, Kees van Berkel, Ad M. G. Peeters, Frits D. Schalij: Asynchronous Multipliers as Combinational Handshake Circuits. 149-163
• 
  Jens Sparsø, Christian D. Nielsen, Lars Skovby Nielsen, Jørgen Staunstrup: Design of Self-timed Multipliers: A Comparison. 165-179
• 
  Jim D. Garside: A CMOS VLSI Implementation of an Asynchronous ALU. 181-192
• 
  Al Davis, Bill Coates, Ken Stevens: Automatic Synthesis of Fast Compact Asynchronous Control Circuits. 193-207
• 
  Kees van Berkel, Ronan Burgess, Joep L. W. Kessels, Marly Roncken, Frits D. Schalij: Characterization and Evaluation of a Compiled Asynchronous IC. 209-221

last updated on Mon May 20 02:15:20 2013 by the dblp team
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