21. ICPP 1992: University of Michigan, An Arbor, Michigan, USA - Volume 1

Trevor N. Mudge (Ed.): Proceedings of the 1992 International Conference on Parallel Processing, August 17-21, 1992, University of Michigan, An Arbor, Michigan, USA. Volume I: Architecture. CRC Press, ISBN 0-8493-0781-3

Caches

Ahmed Louri, Hongki Sung: A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation. 2-9
Serge M. Manning, David G. Meyer: Asynchronous Execution Through Instruction Caching in Massively Parallel Systems. 10-17
Jen-Tien Yen, Behrooz Shirazi, Krishna M. Kavi: A New Cache Coherency and Address Translation Consistency Protocol. 18-21
Ashwini K. Nanda, Laxmi N. Bhuyan: A Formal Specification and Verification Technique for Cache Coherence Protocols. 22-26

Memories

Arun K. Nanda, Lionel M. Ni: MAD Kernels: An Experimental Testbed to Study Multiprocessor Memory System Behvior. 28-35
William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu: Tolerating First Level Memory Access Latency in High-Performance Systems. 36-43
Takeshi Kumagai: Inorder Skew: A Skewing Scheme for Parallel Tree Memories. 44-47
Kay A. Robbins, Steven Robbins: Dynamic Behavior of Memory Reference Streams for the Perfect Club Benchmarks. 48-52
David M. Koppelman: Reducing PE/Memory Traffic in Shared Memory Multiprocessors by the Difference Coding of Addresses. 53-56

MultiComputer Networks I

Youran Lan: Multicast in Faulty Hypercubes. 58-61
Kevin Bolding, Smaragda Konstantinidou: On the Comparison of Hypercube and Torus Networks. 62-66
Smaragda Konstantinidou: Priorities in Nonminimal, Adaptive Routing. 67-71
Rajib K. Das, Krishnendu Mukhopadhyaya, Bhabani P. Sinha: Brdiged and Twisted Hypercubes with Reduced Diameters. 72-75
Ronald Fernandes: Recursive Interconnection Networks for Multicomputer Networks. 76-79
Ke Huang, Jie Wu: Balanced Hypercubes. 80-84

MultiComputer Networks II

Ross E. Johnson, James R. Goodman: Synthesizing General Topologies from Rings. 86-95
Alan Rooks, Bruno R. Preiss: A unifying Framework for Distributed Routing Algorithms. 96-100
Christopher J. Glass, Lionel M. Ni: Maximally Fully Adaptive Routing in 2D Meshes. 101-104
Khaled A. Aly, Patrick W. Dowd: Parallel Computer Reconfigurability Through Optical Interconnects. 105-108

IC Networks

Susan R. Dickey, Ora E. Percus: Performance Differences Among Combining Switch Architectures. 110-117
Hussein M. Alnuweiri, Viktor K. Prasanna: Optimal Multipass Self-Routing Algorithms for Clos-Type Multistage Networks. 118-122
Nabanita Das, Krishnendu Mukhopadhyaya, Jayasree Dattagupta: A Versatile External Control Method for Self-Routable Permutations in Benes Network. 123-126
Brian D. Alleyne, Isaac D. Scherson: Expanded Delta Networks for Verry Large Parallel Computers. 127-131
A. J. Field, Peter G. Harrison: Transmission Times in Unbuffered Crossbars with Cyclic Arbitration. 132-137
Ching-Yi Lee, A. Yavuz Oruç: Design of Efficient and Easily Routable Generalized Connectors. 138-141

Multistage IC Networks

K. Wendy Tang, Sanjay A. Padubidri: Routing and Diameter Analysis of Diagonal Mesh Networks. 143-150
Yeimkuan Chang, Laxmi N. Bhuyan: Extending Multistage Interconnection Networks for Multitasking. 151-158
Akram Abdennadher, Tse-Yun Feng: On Rearrangeability of Omega-Omega Networks. 159-165
Aloke Guha: A Design for Self-Routing Nonblocking Interconnection Networks. 166-169

Instruction Level Parallelism

Takaaki Kato, Koji Suginuma, Nader Bagherzadeh: On Design and Performance Analysis of a Superscalar Architecture. 171-178
Yang-Chang Hong, Chihping Wang: A Tagflow Architecture that Supports Dataflow and Strict-Sequential Instruction Scheduling. 179-187
A. B. Ruighaver: From a Very Long Instruction Word Architecture to a Decoupled Multicomputer Architecture. 188-191
John G. Holm, Prithviraj Banerjee: Low Cost Concurrent Error Detection in a VLIW Architecture Using Replicated Instructions. 192-195
Muhammad F. Mudawwar, C. Y. Roger Chen: The Signal Flow Model: A novel Data Driven Approach to Parallel Processing. 196-200

Communications, Synchronization and Data Mapping

Jeff Baxter, Balkrishna Ramkumar, Janak H. Patel: Compile Time Parallel Resource Allocation for Unbounded Tree Structure Task Graphs. 202-209
Juan Li, Leah H. Jamieson: Algorithm-Architecture Mapping Using Hypergraphs: Theory and Experimental Results. 210-219
Jean-Marc Monti, Guang R. Gao: Efficient Interprocessor Synchronization/Communication on a Dataflow Multiprocessor Architecture. 220-223
Francis P. Augustine, Ravi Varadarajan: Efficient Mappings for Multi-dimensional Systolic Arrays Using Flexible Buffer Structures. 224-227
Martin H. Davis Jr., Umakishore Ramachandran: A Distributed Hardware Barrier in an Optical Bus-Based Distributed Shared Memory Multiprocessor. 228-231

Fault Tolerance

Gene Saghi, Howard Jay Siegel, José A. B. Fortes: On the Viability of a Quantitative Model of System Reconfiguration Due to a Fault. 233-242
Hasan Cam, José A. B. Fortes: Fault-Tolerant Self-Routing Permutation Networks. 243-247
Shakil Akhtar: Reliability of Multiple Bus Multiprocessor Systems. 248-252
Qing Yang, Hong Wang: On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers. 253-256

Miscellaneous Hardware

Evangelos P. Markatos, Thomas J. LeBlanc: Load Balancing vs. Locality Management in Shared-Memory Multiprocessors. 258-267
Ramesh Krishnamurti, Bhagirath Narahari: Preemptive Scheduling of Independent Jobs on Partitionable Parallel Architectures. 268-275
David Smitley, Frank F. Hady, Dan Burns: Hnet: A High-performance Network Evaluation Testbed. 276-279
Samuel A. Fineberg, Thomas L. Casavant: A Preliminary Performance Evaluation of the Seamless Parallel Processing System Architecture. 280-284
Chung-Ho Chen, Arun K. Somani: Effects of Cache Traffic on Shared Bus Multiprocessor Systems. 285-288
Minze V. Chien, A. Yavuz Oruç: Adaptive Binary Sorting Schemes and Associated Interconnection Networks. 289-293

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