ICPP 1987:
University Park, PA, USASession 1:
Compiler Techniques I
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Ron Cytron ,
Jeanne Ferrante :
What's In a Name? -or- The Value of Renaming for Parallelism Detection and Storage Allocation.
19-27
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Session 1B:
Multiprocessor Concurrency
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Stephen A. Brobst :
Organization of an Instruction Scheduling and Token Storage Unit in a Tagged Token Dataflow Machine.
40-46
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Makoto Amamiya :
A New Parallel Graph Reduction Model and Its Machine Architecture.
46-49
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conf/icpp/RasmussenBDLM87
Session 1C :
Algorithm 1
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Session 2A:
Multiprocessor Concurrency
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Session 2B:
Fault Tolerance & Testing
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Yuval Tamir ,
Eli Gafni :
A Software-Based Hardware Fault Tolerance Scheme for Multicomputers.
117-120
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Session 2C:
Data Structures
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Session 3A:
Logic Programming and Systems 1
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conf/icpp/Loganantharaj87 Rasiah Loganantharaj :
Parallel Link Resolution of Connection Graph Refutation and Its Implementation.
154-157
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Session 3B:
Embeddings
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Session 3C:
Graph Algorithms
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Shaunak Pawagi :
Parallel Algorithm for Maximum Weight Matching in Trees.
204-206
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Session 4A:
Compiler Techniques 2
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Ron Cytron :
Limited Processor Scheduling of Doacross Loops.
226-234
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conf/icpp/Polychronopoulos87 export record as
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Session 4B:
Architecture 2
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Alan Norton ,
Evelyn Melton :
A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access.
247-254
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Michel Dubois :
Effect of Invalidations on the Hit Ratio of Cache-Based Multiprocessors.
255-257
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David R. Emberson :
A Cache Coherence Management Technique for Hypercube Multiprocessors.
262-265
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Session 4C:
Algorithms 2
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Session 5A:
Compiler Techniques
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Maya Gokhale :
Exploiting Loop Level Parallelism in Nonprocedural Dataflow Programs.
305-311
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Session 5B:
Architecture 3
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conf/icpp/NishikawaTKYOTTTNHM87 Hiroaki Nishikawa ,
Hiroaki Terada ,
Kohji Komatsu ,
Shin-ichi Yoshida ,
Toshiya Okamoto ,
Yoshiko Tsuji ,
Saki Takakura ,
Tsuyoshi Tokura ,
Yoichiro Nishikawwa ,
Shuji Hara ,
Mitsuo Meichi :
Architecture of a One-Chip Data Driven Processor: Q-p.
319-326
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conf/icpp/AsadaTMMAMSKFS87 export record as
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Session 5C:
Algorithms 3
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Session 6A:
Programming Languages
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Session 6B:
Interconnection Networks 1
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Daeshik Lee :
The Lambda Network: A New Permutation Network.
407-410
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Session 6C:
Numerical Algorithms 1
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David A. Mandell :
Experiences and Results Multitasking a Hydrodynamics Code on Global and Local Memory Machines.
415-420
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Session 7A:
Software Support
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Session 7B:
Interconnection Networks 2
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Alain Jean-Marie :
Re-Routing and Resequencing in Multistage Interconnection Networks.
453-460
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Israel Gazit ,
Miroslaw Malek :
On the Number of Permutations Performable by Extra-Stage Multistage Interconnection Networks.
461-470
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Simin H. Pakzad :
Fault Tolerance Analysis of Rearrangeable Networks.
471-474
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Session 7C:
Numerical Algorithms 2
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Jim Armstrong :
Optimization of Householder Transformations Part I: Linear Least Squares.
495-498
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Session 8a:
Compiler Techniques 4
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Session 8B:
Interconnection Networks 3
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Session 8C:
Systolic Computing I
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Rami G. Melhem :
Iterative Solution of Sparse Linear Systems on Systolic Arrays.
560-563
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Session 9A:
Compiler Techniques 5
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Neal M. Gafter :
Algorithms and Data Structures for Parallel Incremental Parsing.
577-584
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Y. N. Srikant :
Parallel Parsing of Arithmetic Expressions.
589-591
Session 9B:
Architecture 4
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conf/icpp/DimopoulosLWDA87 export record as
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conf/icpp/Barkhordarian87 Shahram Barkhordarian :
RAMPS: A Realtime Structured Small-Scale Data Flow System for Parallel Processing.
610-613
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Session 9C:
Hypercube Computing
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Session 10A:
Software Support 2
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conf/icpp/BolmarcichSDN87 export record as
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Session 10B:
Architecture 5
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conf/icpp/RamachandranSV87 export record as
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Session 10C:
Hypercube Computing
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Session 11A:
Software Support 3
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conf/icpp/EisenstadterMM87
Session 11B:
Interconnection Networks 4
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Vladimir Cherkassky :
A Coding Scheme for Concurrent Error Detection/Correction In Multistage Interconnection Networks.
755-758
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Session 11C:
Image Processing 1
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Session 12A:
Logic Programming & Systems 2
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Session 12B:
Interconnection Networks 5
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A. Yavuz Oruç :
Multistage Permutation Network Design with Double Coset Generators.
824-827
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Session 12C:
Systolic Computing 2
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Session 13A:
Programming Systems
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Session 13B:
Architecture 6
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Session 13C:
Image Processing 2
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Kai Hwang ,
Dongseung Kim :
Parallel Pattern ClusterIng on a Multiprocessor with Orthogonally Shared Memory.
913-916
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