ICCD 1997: Austin, Texas, USA

Session 1.1: Keynote Speech

Session 1.2: CAD Plenary

Session 1.3.1: Special Session: Industrial Application of Formal Verification

(There is no Session 1.3.2)

Session 1.3.3: Simulation and Power Estimation

Session 1.3.4: Branch Prediction

Session 1.4.1: New Techniques for Gate-Sizing and Retiming

Session 1.4.2: Circuit Modeling

Session 1.4.3: Novel Architectures

Short Papers

Session 1.4.4: Low Power Architectures

Session 1.5.1: Timing Optimization for Deep Submicron Technology

Session 1.5.2: Special Session: The G4 S/390 Microprocessor

Session 1.5.3: Multiprocessor Communication

Session 1.5.4: Asynchronous Architectures

Session 1.6.1: Panel: The War of the Roses: Designers versus Tool Developers

Session 1.6.2: Panel: If Software is King for Systems-on-Silicon, What's New in Compilers?

Session 2.1: Design and Test Plenary

Session 2.2.1: Binary Decision Diagrams

Session 2.2.2: Advanced Test Topics

Session 2.2.3: Embedded Software and Systems

Session 2.2.4: Low Power Issues

Session 2.3.1: Formal Verification Methods

Session 2.3.2: Mixed Signal Design and Test

Session 2.3.3: FPGA Design

Session 2.3.4: Cache Technology I

Session 2.4.1: Embedded Tutorial

Session 2.4.2: Fault Diagnosis

Session 2.4.3: Special Session: Low Power Design Issues

Session 2.4.4: Cache Technology II

Session 3.1: Architecture & Algorithm Plenary

Session 3.2.1: Layout Partitioning and Synthesis

Session 3.2.2: Design for Testabiliy & Test Synthesis

Session 3.2.3: Embedded Tutorial

Session 3.2.4: Arithmetics

Session 3.3.1: Asynchronous Design

Session 3.3.2: Special Session: Interconnect Modeling & Repeater Methodologies

Session 3.3.3: Finite-State Machine and High-Level Synthesis

maintained by Schloss Dagstuhl LZI at University of Trier