ICCD 2004: San Jose, CA, USA

Session 1

Session 1.1 High-Speed and Energy-Efficient Circuit Design

Session 1.2 Energy-Efficient Processor Microarchitecture (1)

Session 1.3 Scan Design and Test

Session 2

Session 2.1 Routing and Floorplanning

Session 2.2 Formal Verification Embedded Tutorial

Session 2.3 Signal Integrity and Leakage

Session 3

Session 3.1 Special Session on High-Performance On-Chip Communication.

Session 3.2 Test Generation and Characterization

Session 3.3 Physically-Aware Design Tools

Session 4

Session 4.1 Energy-Efficient Processor Microarchitecture (2)

Session 4.2 Power and Timing Optimization

Session 4.3 Novel Processor Design

Session 5

Session 5.1 Emerging Technologies Special Session

Session 5.2 Cache Memory Design

Session 6

Session 6.1 Layout-Driven Circuit Optimization

Session 6.2 Instruction-Level Parallelism (1)

Session 6.3 Power Estimation and Minimization

Session 7

Session 7.1 Formal Verification Techniques

Session 7.2 Networks on Chips

Session 7.3 Novel Processor Architecture

Session 8

Session 8.1 Instruction-Level Parallelism (2)

Session 8.2 Topics in Synthesis and Co-Simulation

Session 8.3 Low-Power Architecture

Session 9

Session 9.1 Test Generation

Session 9.2 Network Routing

Session 9.3 Placement and Floorplanning

maintained by Schloss Dagstuhl LZI at University of Trier