ICCD 1993: Cambridge, MA, USA

Concurrent Plenary Sessions 1.2.1

CAD Plenary

Concurrent Plenary Sessions 1.2.2

Embedded Systems Plenary

Design and Test Plenary

Concurrent Sessions 1.3

Estimation Techniques for Global Optimization in High-Level Synthesis

Cache Architectures

Design Verification and Modification

Concurrent Sessions 1.4

Timing Anlaysis and Optimization

High Performance General Purpose Machines

Embedded System Architectures

Scan Design

Concurrent Sessions 2.1

Asynchronous Design

Desgin Concepts


Programmable Gate Array Architectures and Systems

Concurrent Sessions 2.2

Formal Methods I

Microprocessor Design

Computer Arithmetic

VLSI Systems

Concurrent Sessions 2.3

Binary Decision Diagrams

Test Generation and Evaluation

Memory Systems

Analysis and Simulation

Concurrent Sessions 2.4

Scheduling Techniques in High-Level Synthesis

Economics of Design and Test

Fine Grain Parallelism

Combinatorial Logic Optimization

Concurrent Sessions 3.1

Formal Methods II

Partitioning and Analysis

Methods and Limitations in CAD Layout

FPGAs for Custom Computing Machines

Concurrent Sessions 3.2

Logic Synthesis

Design for Testability

Reliability Issues

High Level Tools

Concurrent Sessions 3.3

Fault Simulation

Fault Tolerance and Reliability

Signal Processing

maintained by Schloss Dagstuhl LZI at University of Trier