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ORCIDICCD 1991: Cambridge, MA, USA
- Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991. IEEE Computer Society 1991, ISBN 0-8186-2270-9
Keynot Session
- David May:
How to Design a Parallel Computer. 2
VLSI Plenary
- Fritz H. Gaensslen, David D. Meyer:
Liquid Nitrogen CMOS for Computer Applications. 4-8
Architecture Plenary
- E. Scott Kirkpatrick:
Neural Networks Update. 10
Design and Test Plenary
- Vishwani D. Agrawal:
Design and Test-The Two Sides of a Coin. 12
General Purpose Processors
- Yooichi Shintani, Kiyoshi Inoue, Toru Shonai, K. Wada, S. Abe, Katsuro Wakai:
Logic Design for a High Performance Mainframe Computer, The HITAC M-880 Processor. 14-20 - A. Shacham, Y. Levy, Z. Bronstein, E. Loewenstein, D. M. Bruck, D. Deitcher:
Architectural Considerations for SF-core Based Microprocessor. 21-24
Symbolic Layout and Module Generation
- Jürgen Frößl, Bernhard Eschermann:
Module Generation for AND/XOR Fields (XPLAs). 26-29 - Jin-Fuw Lee:
A Layout Compaction Algorithm with Multiple Grid Constraints. 30-33 - Eero Pajarre, Tapani Ritoniemi, Hannu Tenhunen:
Methods and Algorithms for Converting IC Designs Between Incompatible Design Systems. 34-37
IWLS'91: Combinational Optimization
- Yosinori Watanabe, Robert K. Brayton:
Incremental Synthesis for Engineering Changes. 40-43 - Kuang-Chien Chen, Masahiro Fujita:
Concurrent Resynthesis for Network Optimization. 44-48 - Robert F. Damiano, Len Berman:
Dual Global Flow. 49-53
Fault Simulation
- Joan Villoldo, Prathima Agrawal, Vishwani D. Agrawal:
Stafan Algorithms for MOS Circuits. 56-59 - Gianpiero Cabodi, Silvano Gai, Matteo Sonza Reorda
:
Fast Differential Fault Simulation by Dynamic Fault Ordering. 60-63 - John A. Trotter, Richard Evans:
A Fine Grain Architecture for Parallel Fault Simulation. 64-67
IWLS'91: Sequential Optimization
- Sujit Dey, Franc Brglez, Gershon Kedem:
Partitioning Sequential Circuits for Logic Optimization. 70-76 - Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi:
Redundancy Identification and Removal Based on Implicit State Enumeration. 77-80 - Bill Lin, A. Richard Newton:
Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams. 81-85 - Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Retiming of Circuits with Single Phase Transparent Latches. 86-89
Simulation
- F. Sebastiã G. dos Santos, Jacobus W. Swart:
Modeling fo Interconnections Lines for Stimulation of VLSI Circuits. 92-95 - Thomas H. Krodel:
PowerPlay-Fast Dynamic Power Estimation Based on Logic Simulation. 96-100 - Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh:
Parallel Event-Driven Waveform Relaxation. 101-104 - Przemyslaw Bakowski, Jean-Luc Dubois, Adam Pawlak:
A Technique for Generating Efficient Simulators. 105-108
Testing Regular Structures
- Cheng-Wen Wu, Shyue-Kung Lu:
Designing Self-Testable Cellular Arrays. 110-113 - Chin-Long Wey:
Concurrent Error Detection in Array Dividers by Alternating Input Data. 114-117 - Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda:
Testing of Analog Neural Array-Processor Chips. 118-121 - Lon-Chan Chu:
Fault-Tolerant Model of Neural Computing. 122-125
High Performance VLSI Systems
- M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, K. Yano, M. Hiraki, S. Shukuri, T. Nishida:
On-Chip Multiple Superscalar Processors with Secondary Cache Memories. 128-131 - Leith Johnson, Rob Horning, Larry Thayer, Daniel Li, Rob Snyder:
System Level ASIC Design for Hewleet-Packard's Low Cost PA-RISC Workstations. 132-135 - Moshe Shahaf:
DesignFab: A Methodology for ULSI Microprocessor Design. 136-139 - Maximo H. Salinas, Barry W. Johnson, James H. Aylor:
Implementation-Independent Model of an Instruction Set Architecture Using VHDL. 140-145
Panel Session
- George J. Klir:
Fuzzy Logic: Why the U.S. Falls Behind?. ICCD 1991: 148
Monsoon
- Kenneth R. Traub, Gregory M. Papadopoulos, Michael J. Beckerle, James E. Hicks, Jonathan Young:
Overview of the Monsoon Project. 150-155 - Christopher F. Joerg, G. Andrew Boughton:
The Monsoon Interconnection Network. 156-159 - Michael J. Beckerle, Gregory M. Papadopoulos:
Test and Validation for Monsoon Processing Elements. 160-163
Routing Algorithms
- Andrew B. Kahng:
An Effective Analog Approach to Steiner Routing. 166-169 - Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong:
Performance-Driven Global Routing for Cell Based ICs. 170-173 - James P. Cohoon, L. J. Randall:
Critical Net Routing. 174-177
Asynchronous Synthesis
- Hon Fung Li, S. C. Leung, P. N. Lam:
Synthesis of Delay-Insensitive Circuits by Refinements into Atomic Threads. 180-186 - Mark E. Dean, David L. Dill, Mark Horowitz:
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD). 187-191 - Steven M. Nowick, David L. Dill:
Synthesis of Asynchronous State Machines Using A Local Clock. 192-197
Delay Testing
- I. Deol, Chittaranjan Mallipeddi, T. Ramakrishnan:
Amdahl Chip Delay Test System. 200-205 - Patrick C. McGeer:
Robust Path Delay-Fault Testability on Dynamic CMOS Circuits. 206-211 - Abhijit Chatterjee, Manuel A. d'Abreu:
Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs. 212-215
Large-Scale Multiprocessing
- Toshiyuki Tamura, Shinji Komori, Fumiyasu Asai, Hirono Tsubota, Hisakazu Sato, Hidehiro Takata, Yoshihiro Seguchi, Takeshi Tokuda, Hiroaki Terada:
A Data-Driven Architecture for Distributed Parallel Processing. 218-224 - Robert H. Payne, José G. Delgado-Frias:
MPU: A N-Tuple Matching Processor. 225-228 - Massimo Maresca, Pierpaolo Baglietto:
Transitive Closure and Graph Component Labeling on Realistic Processor Arrays Based on Reconfigurable Mesh Network. 229-232 - Hsin-Chou Chi, Yuval Tamir:
Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers. 233-238
Finite State Machine Verification
- Eduard Cerny:
A Compositional Transformation for Formal Verification. 240-244 - Carl Pixley, Gary Beihl, Ernesto Pacas-Skewes:
Automatic Derivation of FSM Specification to Implementation Encoding. 245-249 - Srinivas Devadas, Kurt Keutzer, A. S. Krishnakumar:
Design Verfication and Reachability Analysis Using Algebraic Manipulation. 250-258 - Pranav Ashar, Abhijit Ghosh, Srinivas Devadas:
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. 259-264
Built-In Self Test
- Paul S. Levy:
Power-Down Structures for BIST. 266-269 - Sami A. Al-Arian, Hussam Y. Abujbara, Jim C. Ruel:
A Unique Approach to Built-in-Self-Test Circuit Design. 270-274 - Michael Nicolaidis, M. Boudjit:
New Implementations, Tools, and Experiments for Decreasing Self-Checking PLAs Area Overhead. 275-281 - Scott Chiu, Christos A. Papachristou:
A Built-In Self-Testing Approach for Minimizing Hardware Overhead. 282-285
High Speed Processor Technologies
- Craig Gleason, Mark E. Forsyth, Charlie Kohlhardt, Steve Mangelsdorf, Barry J. Arnold, Rick Luebs:
CMOS Processor Circuit Design in Hewlett-Packard's Series 700 Workstations. 288-292 - C. K. Tien, C. C. Poon, Hans J. Greub, Jack F. McDonald:
F-RISC/I: Fast Reduced Instruction Set Computer with GaAs (H)MESFET Implementation. 293-296 - K. Nah, Robert F. Philhower, J. S. Van Etten, S. Simmons, V. Tsinker, James Loy, Hans J. Greub, Jack F. McDonald:
F-RISC/G: AlGaAs/GaAs HBT Standard Cell Library. 297-300 - Peter R. Nuth, William J. Dally:
A Mechanism for Efficient Context Switching. 301-304
Floorplanning 1
- Klaus Glasmacher, A. Hess, Gerhard Zimmermann:
A Genetic Algorithm for Global Improvement of Macrocell Layouts. 306-313 - Massoud Pedram, Kamal Chaudhary, Ernest S. Kuh:
I/O Pad Assignment Based on the Circuit Structure. 314-318 - Jason Cong, Kei-Yong Khoo:
A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. 319-322
MIPS
- Raymond Peck, Jay Patel:
Design Methodology for a MIPS Compatible Embedded Control Processor. 324-328 - Darren Jones, Rongken Yang, Mark Kwong, George Harper:
Verification Techniques for a MIPS Compatibvle Embedded Control Processor. 329-332 - Bob Culk, Sanjay Desai, Moshe Gavrielov, George Harper, Darren Jones, Mark Kwong, Marlon Murzello, Tim Oke, Jay Patel, Raymond Peck, James Wei, Rongken Yang:
The Architecture of the LR33000: A MIPS Compatible RISC Processor for Embedded Control Applications. 333-336
Formal Verification And Synthesis
- Mark Genoe, Luc J. M. Claesen, Eric Verlind, Frank Proesmans, Hugo De Man:
Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II. 338-341 - Michael C. McFarland, Thaddeus J. Kowalski:
Specifying System Behavior in CPA. 342-345 - Mark D. Aagaard, Miriam Leeser:
A Formally Verified System for Logic Synthesis. 346-350
Signature Analysis And Aliasing
- Geetani Edirisooriya, John P. Robinson:
Aliasing Probability in Multiple Input Linear Signature Automata for Q-ary Symmetric Errors. 352-355 - Anita Gleason, Wen-Ben Jone:
Reduced Hamming Count and Its Aliasing Probability. 356-359 - John C. Chan, Baxter F. Womack, D. F. Wong:
On the Manisfestation of Faults to Errors in Signature Analysis. 360-363
Symbolic Processing
- Atsushi Katsumata, Hidekazu Tokunaga, Seiji Yasunobu:
Operation Method in Fuzzy Set Operation Processor. 366-369 - Vicente Fuentes-Sánchez, Peter Y. K. Cheung:
A Tag Coprocessor Architecture for Symbolic Languages. 370-373 - Chie Dou, Shao-Ming Wu:
An Efficient Pattern Match Architecture for Production Systems Using Content-Addressable Memory. 374-378 - J. Morris Chang, Edward F. Gehringer:
Object-Caching for Performance in Object-Oriented Systems. 379-385
Performance Enhancement
- Pradip Bose:
Early Performance Estimation of Super Scalar Machine Models. 388-392 - Sankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham:
Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. 393-396 - Peter M. Athanas, Harvey F. Silverman:
An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Reconfiguration. 397-400 - Lennart Lindh, Frank Stanischewski:
FASTCHART-Idea and Implementation. 401-404
High Level Synthesis
- Walling R. Cyre:
Mapping Design Knowledge from Multiple Representations. 406-409 - Janaki Akella, Kenneth L. McMillan:
Synthesizing Converters Between Finite State Protocols. 410-413 - Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi:
An Integrated Design Environment for Application Specific Integrated Processor. 414-417 - Chien-In Henry Chen:
Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis. 418-421
Redundancy Issues
- Andrzej Krasniewski, Alexander Albicki:
Random Testability of Redundant Circuits. 424-427 - Gert-Jan Tromp, Ad J. van de Goor:
Logic Synthesis of 100-percent Testable Logic Networks. 428-431 - Rolf Ernst, P. Nowottnick:
Fault Tolerant VLSI Design with Functional Block Redundancy. 432-436
ICCD Banquet
- James D. Meindl:
Design and Test Automation-Gigascale Integration (GSI) in the 21st Century. 438
AS 400
- Quentin G. Schmierer, Andrew H. Wottreng:
IBM AS/400 Processor Architecture and Design Methodology. 440-443 - Robert F. Lembach, John M. Borkenhagen, John R. Elliott, Randall A. Schmidt:
VLSI Design Automation for the Application System/400. 444-447 - Dennis T. Cox, Charles L. Johnson, Bruce G. Rudolph, David W. Siljenberg, Robert R. Williams:
IBM AS/400 Processor Technology. 448-452
Design And Test Automation
- James Pardey, Martin Bolton:
Logic Synthesis of Synchronous Parallel Controllers. 454-457 - Christos A. Papachristou, Scott Chiu, Haidar Harmanani:
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability. 458-462 - Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab:
Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability. 463-466
Interconnect And Packaging
- Chi-Chai Huang, John Willis, Tim Schmitt:
Fine-Line Printed Circuit Board for High-Performance Computer Design. 468-471 - Amit P. Agrawal, Chi Shih Chang, Debra A. Gernhart:
Design Considerations for Digital Circuit Interconnections in a Multilayer Printed Circuit Board. 472-478 - Keith Nabors, S. Kim, Jacob K. White, Stephen D. Senturia:
Fast Capacitance Extraction of General Three-Dimensional Structures. 479-484
Optical Computing
- Walter B. Marvin, Wayne P. Burleson:
A Simulator for General Purpose Optical Arrays. 486-489 - Alex G. Dickinson, M. M. Downs:
An Optical Multichip Module. 490-493 - Joongho Choi, Bing J. Sheu:
A GaAs Receiver Module for Optoelectronic Computing and Interconnection. 494-497
Special Purpose VLSI Architectures
- Shih-Fu Chang, David G. Messerschmitt:
VLSI Designs for High-Speed Huffman Decoder. 500-503 - C. Thomas White, Raj K. Singh, Peter B. Reintjes, Jordan Lampe, Bruce W. Erickson, Wayne D. Dettloff, Vernon L. Chi, Stephen F. Altschul:
BioSCAN: A VLSI-Based System for Biosequence Analysis. 504-509 - Heinz Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai:
VLSI Implementation of a New Block Cipher. 510-513
Floorplanning II
- Cheng-Hsi Chen, Ioannis G. Tollis:
An Optimal Algorithm for Spiral Floorplan Designs. 516-519 - Khe-Sing The, D. F. Wong:
Area Optimization for Higher Order Hierarchical Floorplans. 520-523 - Susmita Sur-Kolay, Bhargab B. Bhattacharya:
The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order. 524-527 - Kyunrak Chong, Sartaj Sahni:
Flipping Modules to Minimize Maximum Wire Length. 528-531
IBM ES/9000 VLSI
- Arnold E. Barish, James P. Eckhardt, Mark D. Mayo, Walter A. Svarczkopf, Santosh P. Gaur, Rao R. Tummala:
High Performance Packaged Electronics for the IBM ES9000TM Mainframe. 534-539 - William J. Nohilly, V. T. Lund:
IBM ES/9000TM System Architecture and Hardware. 540-543 - R. S. Belanger, David P. Conrady, Philip S. Honsinger, T. J. Lavery, Sara J. Rothman, Erich C. Schanzenbach, D. Sitaram, C. R. Selinger, R. E. DuBois, G. W. Mahoney, G. F. Miceli:
Enhanced Chip/Package Design for the IBM ES/9000TM. 544-549 - Brion L. Keller, David A. Haynes:
Design Automation of Test for the EX/9000TM Series Processors. 550-553
Computer Arithmetic
- John A. Harding, Tomás Lang, Jeong-A Lee:
A Comparison of Redundant CORDIC Rotation Engines. 556-559 - N. Burgess:
A Fast Division Algorithm for VLSI. 560-563 - Hosahalli R. Srinivas, Keshab K. Parhi:
High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation. 564-571
Error Checking Schemes
- Behrooz Parhami:
New Classes of Unidirectional Error-Detecting Codes. 574-577 - Niraj K. Jha, Sying-Jyan Wang:
Design and Synthesis of Self-Checking VLSI Circuits and Systems. 578-581 - Stanislaw J. Piestrak:
Design of a Self-Testing Checker for Borden Code. 582-585
Multichip Modules
- Robert F. Miracky, T. Bishop, Claire T. Galanakis, H. Hashemi, Tom J. Hirsch, S. Madere, Heinrich G. Müller, T. Rudwick, L. N. Smith, Scott C. Sommerfeldt, B. Weigler:
Technologies for Rapid Prototyping of Multi-Chip Modules. 588-592 - James B. Burr, Allen M. Peterson:
Energy Considerations in Multichip-Module Based Multiprocessors. 593-600 - Rudi Hendel:
The Commercial Realization of Multi-Chip Modules Quo Vadimus. 601-605
Numeric Processing
- Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi:
High-Performance VLSI Processor for Robot Inverse Dynamics Computation. 608-611 - Ricardo Telichevesky, Prathima Agrawal, John A. Trotter:
A New O(n log n) Scheduling Heuristic for Parallel Decomposition of Sparce Matrices. 612-616 - Liang-Gee Chen, Wai-Ting Chen, Yeu-Shen Jehng, Tzi-Dar Chiueh:
A Predictive Parallel Motion Estimation Algorithm for Digital Image Processing. 617-620 - John A. Trotter, Prathima Agrawal:
A Multiprocessor Architecture for Circuit Simulation. 621-625
Random Thoughts In Logic Synthesis
- Abdul A. Malik, David Harrison, Robert K. Brayton:
Three-Level Decomposition with Application to PLDs. 628-633 - Jonathan Saul:
An Algorithm for the Multi-Level Minimazation of Reed-Muller Rpresentations. 634-637 - Yun-Cheng Ju, Resve A. Saleh:
Identification of Viable Paths Using Binary Decision Diagrams. 638-641 - Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson:
Optimal Clocking of Circular Pipelines. 642-650
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