ICCAD 2010: San Jose, California, USA
2010 International Conference on Computer-Aided Design (ICCAD'10), November 7-11, 2010, San Jose, CA, USA. IEEE 2010
Fast and Accurate System Estimation, Evaluation, and Optimization
- Karthick Parashar, Daniel Menard, Romuald Rocher, Olivier Sentieys, David Novo, Francky Catthoor: Fast performance evaluation of fixed-point systems with un-smooth operators. 9-16
- Gregory Lucas, Deming Chen: Variation-aware layout-driven scheduling for performance yield optimization. 17-24
Manufacturing-Aware Design
- Vivek Joshi, Kanak Agarwal, David Blaauw, Dennis Sylvester: Analysis and optimization of SRAM robustness for double patterning lithography. 25-31
- Kun Yuan, David Z. Pan: WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography. 32-38
- Xin Li: Maximum-information storage system: Concept, implementation and application. 39-46
- Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar: Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation. 47-54
Analog and Mixed Signal Verification and Optimization
- Amandeep Singh, Peng Li: On behavioral model equivalence checking for large analog/mixed signal systems. 55-61
- Ashish Kumar Singh, Mario Lok, Kareem Ragab, Constantine Caramanis, Michael Orshansky: An algorithm for exploiting modeling error statistics to enable robust analog optimization. 62-69
- Guoyong Shi: A simple implementation of determinant decision diagram. 70-76
Designing for Uncertainty: Addressing Process Variations and Aging Issues in Digital Systems
- Keith A. Bowman, James W. Tschanz: Resilient microprocessor design for improving performance and energy efficiency. 85-88
- Siddharth Garg, Diana Marculescu, Sebastian Herbert: Process variation aware performance modeling and dynamic power management for multi-core systems. 89-92
Design-Aware Manufacturing
- Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald: Design-aware mask inspection. 93-99
- Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky: SMATO: Simultaneous mask and target optimization for improving lithographic process window. 100-106
- Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif: Template-mask design methodology for double patterning technology. 107-111
- Wai-Shing Luk, Huiping Huang: Fast and lossless graph division method for layout decomposition using SPQR-tree. 112-115
- Tuck-Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta: Design dependent process monitoring for back-end manufacturing cost reduction. 116-122
Advances in Embedded Systems and FPGA Synthesis
- Nabeel Iqbal, Jörg Henkel: SETS: Stochastic execution time scheduling for multicore systems by joint state space and Monte Carlo. 123-130
- Simon Perathoner, Kai Lampka, Nikolay Stoimenov, Lothar Thiele, Jian-Jia Chen: Combining optimistic and pessimistic DVS scheduling: An adaptive scheme and analysis. 131-138
- Hessam Kooti, Eli Bozorgzadeh: Unified theory of real-time task scheduling and dynamic voltage/frequency Scaling on MPSoCs. 139-142
Enhancing Test for Delays and Opens under Power-Sensitive Conditions
- Zhen Chen, Krishnendu Chakrabarty, Dong Xiang: MVP: Capture-power reduction with minimum-violations partitioning for delay testing. 149-154
- Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai: Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. 155-161
- Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli: A scalable quantitative measure of IR-drop effects for scan pattern generation. 162-167
- Hamid Shojaei, Azadeh Davoodi: Trace signal selection to enhance timing and logic visibility in post-silicon validation. 168-172
Reliability Analysis and Optimization at System Level: A Straddle between Complexity and Accuracy
- Anne Gattiker: System-level impact of chip-level failure mechanisms and screens. 173-176
- Larkhoon Leem, Hyungmin Cho, Hsiao-Heng Lee, Young Moon Kim, Yanjing Li, Subhasish Mitra: Cross-layer error resilience for robust systems. 177-180
- Robert P. Dick: Reliability, thermal, and power modeling and optimization. 181-184
- Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich: Symbolic system level reliability analysis. 185-189
Advanced Scheduling for Memory Systems
- Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang: Hierarchical memory scheduling for multimedia MPSoCs. 190-196
- Zefu Dai, Mark Jarvin, Jianwen Zhu: Credit Borrow and Repay: Sharing DRAM with minimum latency and bandwidth guarantees. 197-204
- Weijia Che, Karam S. Chatha: Scheduling of synchronous data flow models on scratchpad memory based embedded processors. 205-212
Making Critical Decision on Power in Physical Synthesis
- Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen: Post-placement power optimization with multi-bit flip-flops. 218-223
- Manu Jose, Yu Hu, Rupak Majumdar: On power and fault-tolerance optimization in FPGA physical synthesis. 224-229
Advances in Yield and Quality Analysis
- Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin: Mathematical yield estimation for two-dimensional-redundancy memory arrays. 235-240
- Haralampos-G. D. Stratigopoulos, Salvador Mir: Analog test metrics estimates with PPM accuracy. 241-247
Analog Challenges in Nanometer CMOS and Digitalization of Analog Functionality
- Georges G. E. Gielen, Elie Maricau, Peter H. N. De Wit: Design automation towards reliable analog integrated circuits. 248-251
- Stephan Henzler: Digitalization of mixed-signal functionality in nanometer technologies. 252-255
Design Optimization for Power-Efficient Synchronous and Asynchronous Systems
- Andrew B. Kahng, Bill Lin, Kambiz Samadi, Rohit Sunkam Ramanujam: Efficient trace-driven metaheuristics for optimization of networks-on-chip configurations. 256-263
- Jin Sun, Rui Zheng, Jyothi Velamala, Yu Cao, Roman L. Lysecky, Karthik Shankar, Janet Meiling Wang Roveda: A self-evolving design methodology for power efficient multi-core systems. 264-268
- John Hansen, Montek Singh: An energy and power-aware approach to high-level synthesis of asynchronous systems. 269-276
- Yifang Liu, Yu Yang, Jiang Hu: Clustering-based simultaneous task and voltage scheduling for NoC systems. 277-283
Improving Simulation Performance
- Chenjie Gu, Jaijeet S. Roychowdhury: Generalized nonlinear timing/phase macromodeling: Theory, numerical methods and applications. 284-291
- Alper Demir, Chenjie Gu, Jaijeet S. Roychowdhury: Phase equations for quasi-periodic oscillators. 292-297
Advances in Global Routing
- Tsung-Hsien Lee, Ting-Chi Wang: Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing. 312-318
- Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang: GLADE: A modern global router considering layer directives. 319-323
System Level Design - An Industrial Perspective
- Guido Stehr, Josef Eckmuuller: Transaction level modeling in practice: Motivation and introduction. 324-331
- Laurent Maillet-Contoz: Standards for System Level Design. 332-335
- Sören Sonntag, Francisco Gilabert Villamón: Design space exploration and performance evaluation at Electronic System Level for NoC-based MPSoC. 336-339
- Enno Wein: HW/SW co-design of parallel systems. 344-348
- Achim Nohl, Frank Schirrmeister, Drew Taussig: Application specific processor design: Architectures, design methods and tools. 349-352
System-Level Static and Dynamic Low Power Design
- Muhammad Shafique, Lars Bauer, Jörg Henkel: Selective instruction set muting for energy-aware adaptive processors. 353-360
- Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim: Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors. 361-364
- Xi Chen, Chi Xu, Robert P. Dick: Memory access aware on-line voltage control for performance and energy optimization. 365-372
Leveraging Logics, Wire and 3D for Physical Synthesis
- David A. Papa, Smita Krishnaswamy, Igor L. Markov: SPIRE: A retiming-based physical-synthesis transformation system. 373-380
- Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang: Redundant-wires-aware ECO timing and mask cost optimization. 381-386
- Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Kyu Lim: Through-silicon-via management during 3D physical design: When to add and how many? 387-394
Beyond-Die Designs: Solutions and Challenges
- John F. Park: Board driven I/O planning & optimization. 395-397
Advances in Biological and Post-CMOS Systems
- Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, Keshab K. Parhi: A synthesis flow for digital signal processing with biomolecular reactions. 417-424
- Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho: A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chips. 425-431
- Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang: Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement. 432-437
Pushing Clock Distribution Performance
- Minsik Cho, David Z. Pan, Ruchir Puri: Novel binary linear programming for high performance clock mesh synthesis. 438-443
- Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang: High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees. 452-457
- Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young: Local clock skew minimization using blockage-aware mixed tree-mesh clock network. 458-462
3D-ICs and Detection of Faults and Hardware Trojans
- Arvind Sridhar, Alessandro Vincenzi, Martino Ruggiero, Thomas Brunschwiler, David Atienza: 3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling. 463-470
- Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty: Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. 471-476
- Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie: Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip. 477-482
- Sheng Wei, Miodrag Potkonjak: Scalable segmentation-based malicious circuitry detection and diagnosis. 483-486
- Andrea Pellegrini, Valeria Bertacco: Application-Aware diagnosis of runtime hardware faults. 487-492
Organic Electronics
- Hagen Klauk, Ute Zschieschang: Manufacturing and characteristics of low-voltage organic thin-film transistors. 493-495
- Jan Genoe, Kris Myny, Soeren Steudel, Paul Heremans: Design and manufacturing of organic RFID circuits: Coping with intrinsic parameter variations in organic devices by circuit design. 496-499
- Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai: Design of large area electronics with organic transistors. 500-503
Advances in Timing Analysis
- Cheng Zhuo, Kanak Agarwal, David Blaauw, Dennis Sylvester: Active learning framework for post-silicon variation extraction and test cost reduction. 508-515
- Lu Wan, Deming Chen: Analysis of circuit dynamic behavior with timed ternary decision diagram. 516-523
- Bing Li, Ning Chen, Ulf Schlichtmann: Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods. 524-531
Parallel Methods for Power Grid and Interconnect Analysis
- Jorge Fernandez Villena, Luis Miguel Silveira: 3POr - Parallel projection based parameterized order reduction for multi-dimensional linear models. 536-542
- Xuanxing Xiong, Jia Wang: A hierarchical matrix inversion algorithm for vectorless power grid verification. 543-550
Physical Design for Manufacturability and Variability
- Szu-Yu Chen, Yao-Wen Chang: Native-conflict-aware wire perturbation for double patterning technology. 556-561
- Vineeth Veetil, Dennis Sylvester, David Blaauw: A lower bound computation method for evaluation of statistical design techniques. 562-569
- Shantanu Dutt, Huan Ren: Timing yield optimization via discrete gate sizing using globally-informed delay PDFs. 570-577
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
- Tsung-Yi Ho, Jun Zeng, Krishnendu Chakrabarty: Digital microfluidic biochips: A vision for functional diversity and more than moore. 578-585
Advances in Core Logic Synthesis
- Mihir R. Choudhury, Kartik Mohanram: Bi-decomposition of large Boolean functions using blocking edge graphs. 586-591
- Junjun Gu, Gang Qu, Lin Yuan, Qiang Zhou: Peak current reduction by simultaneous state replication and re-encoding. 592-595
- Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang: Boolean matching of function vectors with strengthened learning. 596-601
Routing - Theory and Practice
- Tao Huang, Evangeline F. Y. Young: Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach. 610-613
- Tan Yan, Pei-Ci Wu, Qiang Ma, Martin D. F. Wong: On the escape routing of differential pairs. 614-620
- Taraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew D. Huber, Shyam Ramji: New placement prediction and mitigation techniques for local routing congestion. 621-624
Power Optimization from Systems to Circuits
- Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai: Misleading energy and performance claims in sub/near threshold digital systems. 625-631
- Hao Xu, Wen-Ben Jone, Ranga Vemuri: Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. 632-636
- Hao Xu, Ranga Vemuri, Wen-Ben Jone: Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. 637-641
Manufacturing, CAD and Thermal-Aware Architectures for 3-D MPSoCs
- Mohamed M. Sabry, Ayse Kivilcim Coskun, David Atienza: Fuzzy control for enforcing energy efficiency in high-performance 3D systems. 642-648
Algorithms for Placement: Full House
- Meng-Kai Hsu, Yao-Wen Chang: Unified analytical global placement for large-scale mixed-size circuit designs. 657-662
- Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan: Design-hierarchy aware mixed-size placement for routability optimization. 663-668
- Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim: Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. 669-674
- Linfu Xiao, Evangeline F. Y. Young, Xiaoyong He, K. P. Pun: Practical placement and routing techniques for analog circuit designs. 675-679
Analysis and Algorithms for Design and Test in 3D and Many-Core Systems
- Le Yu, Haigang Yang, Tom T. Jing, Min Xu, Robert E. Geer, Wei Wang: Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICs. 686-693
- Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay: Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. 694-697
Advanced Analysis of Circuit/Device Reliability
- Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. 703-708
- Yun Ye, Chi-Chao Wang, Yu Cao: Simulation of random telegraph Noise with 2-stage equivalent circuit. 709-713
- Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee: Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design. 714-720
- Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake: Structured analog circuit design and MOS transistor decomposition for high accuracy applications. 721-728
Advanced Applications of Logic Synthesis
- Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang: A robust functional ECO engine by SAT proof minimization and interpolation techniques. 729-734
- Vinay Karkala, Joseph Wanstrath, Travis Lacour, Sunil P. Khatri: Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT. 735-738
- O. Sarbishei, Katarzyna Radecka: Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits. 739-745
- Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang: Synthesis of an efficient controlling structure for post-silicon clock skew minimization. 746-749
- Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong: Engineering a scalable Boolean matching based on EDA SaaS 2.0. 750-755
- Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler: Polynomial datapath optimization using constraint solving and formal modelling. 756-761
Advances in Verification
- Po-Hsien Chang, Dragoljub Gagi Drmanac, Li-C. Wang: Online selection of effective functional test programs based on novelty detection. 762-769
- Roberto Bruttomesso, Simone Rollini, Natasha Sharygina, Aliaksei Tsitovich: Flexible interpolation with local proof transformations. 770-777
- Marc Galceran Oms, Jordi Cortadella, Michael Kishinevsky: Symbolic performance analysis of elastic systems. 778-785
- Malay K. Ganai, Chao Wang, Weihong Li: Efficient state space exploration: Interleaving stateless and state-based model checking. 786-793
- Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang Huang: Formal deadlock checking on high-level SystemC designs. 794-799
Recent Advances in Power Grid and Interconnect Analysis
- Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K. H. Pang, Ngai Wong: PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation. 800-807
- Nestoras E. Evmorfopoulos, Maria-Aikaterini Rammou, George I. Stamoulis, John Moondanos: Characterization of the worst-case current waveform excitations in general RLC-model power grid analysis. 824-830
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last updated on 2013-06-19T201401 by the dblp team