ICCAD 2003:
San Jose, California, USA
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conf/iccad/SwaminathanC03 export record as
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Shaoxiong Hua ,
Gang Qu :
Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages.
26-29
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Le Yan ,
Jiong Luo ,
Niraj K. Jha :
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems.
30-38
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conf/iccad/SrivastavaMCS03 export record as
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Brian Swahn ,
Soha Hassoun :
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading.
58-65
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conf/iccad/MamidipakaKDA03 export record as
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conf/iccad/NadezhinGGEZBPBAP03 export record as
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conf/iccad/BernsteinCJP03 export record as
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Junhyung Um ,
Taewhan Kim :
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design.
197-200
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Jinfeng Liu ,
Pai H. Chou :
Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning.
201-208
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Ruibing Lu ,
Cheng-Kok Koh :
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels.
227-231
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Fabrice Veersé :
Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation.
251-255
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conf/iccad/AgnihotriYKMOM03 export record as
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conf/iccad/MarculescuZSM03 export record as
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conf/iccad/Taherzadeh-SaniLS03 export record as
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Alper Demir :
Noise Analysis for Optical Fiber Communication Systems.
441-445
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conf/iccad/RaychowdhuryMR03 export record as
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conf/iccad/MahapatraBPI03 export record as
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conf/iccad/StammermannHSSN03 export record as
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conf/iccad/KhandelwalDNS03 export record as
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Weiping Liao ,
Lei He :
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion.
574-580
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conf/iccad/NicolaidisAB03 export record as
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conf/iccad/Stanley-MarbellM03 export record as
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Sheldon X.-D. Tan :
A General S-Domain Hierarchical Network Reduction Algorithm.
650-657
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conf/iccad/SelvakkumaranK03 export record as
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Zhao Li ,
C.-J. Richard Shi :
SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects.
793-800
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Irith Pomeranz ,
Sudhakar M. Reddy :
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic.
867-873
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