ICCAD 2001:
San Jose, California, USADynamic Verification
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System-Level Exploration and Design
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Interconnect Planning
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Analog Macromodeling
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Embedded Tutorial:
Platform-Based Designs
Embedded Tutorial:
VLSI Microsystems:
The Power of Many
Sequential Synthesis
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conf/iccad/YevtushenkoVBPS01
Compiler Techniques in System Level Design
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Routing Architecture and Techniques for FPGAs
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Vinay Verma ,
Shantanu Dutt :
A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs.
144-
Interconnect Performance and Reliability Optimization
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Panel
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conf/iccad/KuehlmannDFGLPT01
Circuit Structure in Fromal Verification
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conf/iccad/BaumgartnerK01 export record as
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System Level Power and Performance Modeling
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conf/iccad/BeltrameBFSST01 export record as
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conf/iccad/MarculescuNLS01
Topics in Physical Synthesis
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conf/iccad/KutzschebauchS01 export record as
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Model Order Reduction
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Michal Rewienski ,
Jacob White :
A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices.
252-
Embedded Tutorial:
Embedded Software and Systems
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Niraj K. Jha :
Low Power System Scheduling and Synthesis.
259-263
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Lothar Thiele :
Integral Design Representations for Embedded Systems.
264
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Embedded Tutorial
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BDDs and SAT
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conf/iccad/ChauhanCJKSVW01
Convergence of Abstractions in High-Level Synthesis
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conf/iccad/PeymandoustM01 export record as
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Signal Integrity and Clock Design
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James D. Z. Ma ,
Lei He :
Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering.
327-332
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Yonghee Im ,
Kaushik Roy :
CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic.
337-
Analog Synthesis
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conf/iccad/KrasnickiPHMRC01 export record as
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conf/iccad/VancorenlandPSGS01
Manufacturing Test:
Stuck-at to Crosstalk
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Architecture Oriented Scheduling
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conf/iccad/Alba-PintoMJ01 export record as
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New Techniques in Routing
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Issues in Substrate Coupling
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Joe Kanapka ,
Jacob White :
Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank Approximation.
417-423
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Combinational Optimization
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Real Time Scheduling and Performance Analysis
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Felice Balarin :
Stars in VCC: Complementing Simulation with Worst-Case Analysis.
471-
Power Analysis
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Timing and Noise Analysis
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System Level Test and Reliability
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Kaijie Wu ,
Ramesh Karri :
Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique.
537-
Power Issues in High Level Synthesis
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conf/iccad/RaghunathanRRL01 export record as
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Gang Qu :
What is the Limit of Energy Saving by Dynamic Voltage Scaling?
560-
Advances in Placement
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conf/iccad/GopalakrishnanR01
Interconnect Analysis and Extraction
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Payam Heydari ,
Massoud Pedram :
Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation.
586-591
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Don't Care Optimization and Boolean Matching
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Jovanka Ciric ,
Carl Sechen :
Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries.
610-617
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Power Saving Techniques for Embedded Processors
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conf/iccad/HoffmannSNBWM01 export record as
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conf/iccad/ParameswaranH01 Sri Parameswaran ,
Jörg Henkel :
I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency.
635-
Embedded Tutorial:
IC Power Distribution Challenges
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Panel
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conf/iccad/RutenbarCGKPRS01
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