International Conference on Computer-Aided Design, November 4-8, 2001, San Jose, CA, USA. ACM, 2001
San Jose, California, USA
System-Level Exploration and Design
The Power of Many
Compiler Techniques in System Level Design
Routing Architecture and Techniques for FPGAs
Interconnect Performance and Reliability Optimization
Circuit Structure in Fromal Verification
System Level Power and Performance Modeling
Topics in Physical Synthesis
Model Order Reduction
Embedded Software and Systems
Niraj K. Jha
: Low Power System Scheduling and Synthesis.
: Integral Design Representations for Embedded Systems.
BDDs and SAT
Convergence of Abstractions in High-Level Synthesis
Signal Integrity and Clock Design
James D. Z. Ma
, Lei He
: Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering.
, Kaushik Roy
: CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic.
Stuck-at to Crosstalk
Architecture Oriented Scheduling
New Techniques in Routing
Issues in Substrate Coupling
, Jacob White
: Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank Approximation.
Real Time Scheduling and Performance Analysis
: Stars in VCC: Complementing Simulation with Worst-Case Analysis.
Timing and Noise Analysis
System Level Test and Reliability
, Ramesh Karri
: Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique.
Power Issues in High Level Synthesis
Advances in Placement
Interconnect Analysis and Extraction
, Massoud Pedram
: Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation.
Don't Care Optimization and Boolean Matching
Power Saving Techniques for Embedded Processors
IC Power Distribution Challenges