ICCAD 2000:
San Jose, California, USAEllen Sentovich (Ed.):
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000.
IEEE 2000, ISBN 0-7803-6448-1 Floorplanning and Partitioning
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Florin Balasa :
Modeling Non-Slicing Floorplans with Binary Trees.
13-16
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High Level Simulation
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Peter M. Maurer :
Event Driven Simulation Without Loops or Conditionals.
23-26
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Methods for DSP Synthesis and Debugging
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conf/iccad/KoushanfarKP00 export record as
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conf/iccad/KjeldsbergCA00 export record as
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Issues in Timing Estimation
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conf/iccad/OrshanskyMCKH00 export record as
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Embedded Tutorial
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Embedded Tutorial
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Topics in Routing
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Partial Verification Techniques
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conf/iccad/GovindarajuD00 export record as
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C. Norris Ip :
Simulation Coverage Enhancement Using Test Stimulus Transformations.
127-133
Scheduling and Compilation for Embedded Systems
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conf/iccad/ZiegenbeinUE00
Inductance and Full-Wave Analysis
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Placement I
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High-Level Design Tools for Analog Circuits
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Delay Budgeting and Distribution
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Interconnect Analysis
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Embedded Tutorial
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Embedded Tutorial
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Placement II
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Ke Zhong ,
Shantanu Dutt :
Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views.
254-259
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Analog and RF Simulation
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Baolin Yang ,
Dan Feng :
Efficient Finite-Difference Method for Quasi-Periodic Steady-State and Small Signal Analyses.
272-276
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Markovian Analysis and Asynchronous Circuits
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Alper Demir ,
Peter Feldmann :
Modelling and Analysis of Communication Circuit Performance Using Markov Chains and Efficient Graph Representations.
290-295
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Sangyun Kim ,
Peter A. Beerel :
Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm.
296-302
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Low Power Interconnect Modeling and Optimization
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Panel
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conf/iccad/BechtolsheimCGSS00
Static Timing Analysis
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conf/iccad/KulshreshthaPMBY00
Embedded Systems Power Management and Validation
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conf/iccad/RamanathanIG00 export record as
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Jiong Luo ,
Niraj K. Jha :
Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems.
357-364
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Advances in Layout and Synthesis
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Rajeev Murgai :
Layout-Driven Area-Constrained Timing Optimization by Net Buffering.
379-386
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Embedded Tutorial
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Noise and Performance Issues in Routing
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Communication Architectures Design and Analysis
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Performance Driven Logic Synthesis
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conf/iccad/KutzschebauchS00 export record as
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conf/iccad/SrivastavaKS00 export record as
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New Approaches to At-Speed BIST and Diagnosis
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Power Analysis and Optimization
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VLIW Exploration and Design Synthesis
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Flexibility in Logic Synthesis
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Digital and Analog Test Generation
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conf/iccad/ChakrabartiC00
Embedded Tutorial
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conf/iccad/NachtergaeleTD00
Embedded Tutorial
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