11. HPCA 2005:
San Francisco, CA, USA Keynote
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Fred Weber :
Trends in High-Performance Processors.
3
Processor Architecture
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conf/hpca/BalasubramonianMRV05 export record as
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Temperature, Energy, and Power
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Communication Architectures
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Energy and Power
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Memory System Issues
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Aamer Jaleel ,
Bruce L. Jacob :
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions.
191-200
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Zhichun Zhu ,
Zhao Zhang :
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors.
213-224
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Industrial Perspectives (I)
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conf/hpca/JacobsonBHBZEEGLST05 Hans M. Jacobson ,
Pradip Bose ,
Zhigang Hu ,
Alper Buyuktosunoglu ,
Victor V. Zyuban ,
Richard J. Eickemeyer ,
Lee Eisen ,
John Griswell ,
Doug Logan ,
Balaram Sinharoy ,
Joel M. Tendler :
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
238-242
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Industrial Perspectives (II)
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H. Peter Hofstee :
Power Efficient Processor Architecture and The Cell Processor.
258-262
Panel:
New Opportunities for Computer Architecture Research:
An Industrial Perspective
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Evaluation Methodologies
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Software Debugging Support
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Feng Qin ,
Shan Lu ,
Yuanyuan Zhou :
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs.
291-302
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Multiprocessors and Multithreading
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