10. HPCA 2004: Madrid, Spain

Power Management

• Victor Wen, Mark Whitney, Yatish Patel, John Kubiatowicz:
  Exploiting Prediction to Reduce Power on Buses. 2-13
  
• Jian Li, José F. Martínez, Michael C. Huang:
  The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors. 14-23
  
• Chris Gniady, Y. Charlie Hu, Yung-Hsiang Lu:
  Program Counter Based Techniques for Dynamic Power Management. 24-35
  
• Russ Joseph, Zhigang Hu, Margaret Martonosi:
  Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization. 36-47
  

Processor Design I

• Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero:
  Out-of-Order Commit Processors. 48-59
  
• Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally:
  Stream Register Files with Indexed Access. 60-72
  
• Jaume Abella, Antonio González:
  Low-Complexity Distributed Issue Queue. 73-83
  

Prefetching

• Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen:
  Hardware Support for Prescient Instruction Prefetch. 84-95
  
• Kyle J. Nesbit, James E. Smith:
  Data Cache Prefetching Using a Global History Buffer. 96-105
  
• Spiros Kalogeropulos, Mahadevan Rajagopalan, Vikram Rao, Yonghong Song, Partha Tirumalai:
  Processor Aware Anticipatory Prefetching in Loops. 106-117
  

I/O

• Qingbo Zhu, Francis M. David, Christo Frank Devaraj, Zhenmin Li, Yuanyuan Zhou, Pei Cao:
  Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management. 118-129
  
• Enrique V. Carrera, Ricardo Bianchini:
  Improving Disk Throughput in Data-Intensive Servers. 130-141
  
• Jianyong Zhang, Anand Sivasubramaniam, Hubertus Franke, Natarajan Gautam, Yanyong Zhang, Shailabh Nagar:
  Synthesizing Representative I/O Workloads for TPC-H. 142-151
  
• Srihari Makineni, Ravi R. Iyer:
  Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor. 152-163
  

Caches & Memory I

• Lu Peng, Jih-Kwon Peir, Konrad Lai:
  Signature Buffer: Bridging Performance Gap between Registers and Caches. 164-175
  
• Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemir:
  Organizing the Last Line of Defense before Hitting the Memory Wall for CMP. 176-185
  
• Pierre Michaud:
  Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration. 186-197
  

Scheduling

• Ilhyun Kim, Mikko H. Lipasti:
  Understanding Scheduling Replay Schemes. 198-209
  
• Satish Narayanasamy, Yuanfang Hu, Suleyman Sair, Brad Calder:
  Creating Converged Trace Schedules Using String Matching. 210-221
  
• Todd E. Ehrhart, Sanjay J. Patel:
  Reducing the Scheduling Critical Cycle Using Wakeup Prediction. 222-231
  
• Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Exploring Wakeup-Free Instruction Scheduling. 232-243
  

Processor Design II

• Ayose Falcón, Alex Ramírez, Mateo Valero:
  A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. 244-253
  
• Amit Gandhi, Haitham Akkary, Srikanth T. Srinivasan:
  Reducing Branch Misprediction Penalty via Selective Branch Recovery. 254-264
  
• Haitham Akkary, Srikanth T. Srinivasan, Rajendar Koltur, Yogesh Patil, Wael Refaai:
  Perceptron-Based Branch Confidence Estimation. 265-275
  

Caches & Memory II

• Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas Moshovos:
  Accurate and Complexity-Effective Spatial Pattern Prediction. 276-287
  
• Mazen Kharbutli, Keith Irwin, Yan Solihin, Jaejin Lee:
  Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses. 288-299
  
• Manel Fernández, Roger Espasa:
  Link-Time Path-Sensitive Memory Redundancy Elimination. 300-310
  

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